Commit 688486a4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.6-2020-01-10-dp-mst-dsc' of... 

Merge tag 'amd-drm-next-5.6-2020-01-10-dp-mst-dsc' of git://people.freedesktop.org/~agd5f/linux

 into drm-next

amd-drm-next-5.6-2020-01-10-dp-mst-dsc:

drm:
- Add MST helper for PBN calculation of DSC modes
- Parse FEC caps on MST ports
- Add MST DPCD R/W functions
- Add MST helpers for virtual DPCD aux
- Add MST HUB quirk
- Add MST DSC enablement helpers

amdgpu:
- Enable MST DSC
- Add fair share algo for DSC bandwidth calcs
- Fix for 32 bit builds

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200110214328.308549-1-alexander.deucher@amd.com
parents d5d88cd6 485b747e

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+114 −7
Original line number Diff line number Diff line
@@ -4933,12 +4933,13 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 
								    is_y420);

		bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;

		clock = adjusted_mode->clock;

		dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp);

		dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);

	}

	dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,

									   mst_mgr,

									   mst_port,

									   dm_new_connector_state->pbn);

									   dm_new_connector_state->pbn,

									   0);

	if (dm_new_connector_state->vcpi_slots < 0) {

		DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);

		return dm_new_connector_state->vcpi_slots;
@@ -4951,6 +4952,71 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 
	.atomic_check = dm_encoder_helper_atomic_check

};



#if defined(CONFIG_DRM_AMD_DC_DCN)

static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,

					    struct dc_state *dc_state)

{

	struct dc_stream_state *stream = NULL;

	struct drm_connector *connector;

	struct drm_connector_state *new_con_state, *old_con_state;

	struct amdgpu_dm_connector *aconnector;

	struct dm_connector_state *dm_conn_state;

	int i, j, clock, bpp;

	int vcpi, pbn_div, pbn = 0;



	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {



		aconnector = to_amdgpu_dm_connector(connector);



		if (!aconnector->port)

			continue;



		if (!new_con_state || !new_con_state->crtc)

			continue;



		dm_conn_state = to_dm_connector_state(new_con_state);



		for (j = 0; j < dc_state->stream_count; j++) {

			stream = dc_state->streams[j];

			if (!stream)

				continue;



			if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)

				break;



			stream = NULL;

		}



		if (!stream)

			continue;



		if (stream->timing.flags.DSC != 1) {

			drm_dp_mst_atomic_enable_dsc(state,

						     aconnector->port,

						     dm_conn_state->pbn,

						     0,

						     false);

			continue;

		}



		pbn_div = dm_mst_get_pbn_divider(stream->link);

		bpp = stream->timing.dsc_cfg.bits_per_pixel;

		clock = stream->timing.pix_clk_100hz / 10;

		pbn = drm_dp_calc_pbn_mode(clock, bpp, true);

		vcpi = drm_dp_mst_atomic_enable_dsc(state,

						    aconnector->port,

						    pbn, pbn_div,

						    true);

		if (vcpi < 0)

			return vcpi;



		dm_conn_state->pbn = pbn;

		dm_conn_state->vcpi_slots = vcpi;

	}

	return 0;

}

#endif



static void dm_drm_plane_reset(struct drm_plane *plane)

{

	struct dm_plane_state *amdgpu_state = NULL;
@@ -7829,6 +7895,29 @@ cleanup: 
	return ret;

}



static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)

{

	struct drm_connector *connector;

	struct drm_connector_state *conn_state;

	struct amdgpu_dm_connector *aconnector = NULL;

	int i;

	for_each_new_connector_in_state(state, connector, conn_state, i) {

		if (conn_state->crtc != crtc)

			continue;



		aconnector = to_amdgpu_dm_connector(connector);

		if (!aconnector->port || !aconnector->mst_port)

			aconnector = NULL;

		else

			break;

	}



	if (!aconnector)

		return 0;



	return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);

}



/**

 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.

 * @dev: The DRM device
@@ -7881,6 +7970,16 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 
	if (ret)

		goto fail;



	if (adev->asic_type >= CHIP_NAVI10) {

		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {

			if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {

				ret = add_affected_mst_dsc_crtcs(state, crtc);

				if (ret)

					goto fail;

			}

		}

	}



	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {

		if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&

		    !new_crtc_state->color_mgmt_changed &&
@@ -7984,11 +8083,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 
	if (ret)

		goto fail;



	/* Perform validation of MST topology in the state*/

	ret = drm_dp_mst_atomic_check(state);

	if (ret)

		goto fail;



	if (state->legacy_cursor_update) {

		/*

		 * This is a fast cursor update coming from the plane update
@@ -8057,6 +8151,15 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 
		if (ret)

			goto fail;



#if defined(CONFIG_DRM_AMD_DC_DCN)

		if (!compute_mst_dsc_configs_for_state(state, dm_state->context))

			goto fail;



		ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);

		if (ret)

			goto fail;

#endif



		if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {

			ret = -EINVAL;

			goto fail;
@@ -8085,6 +8188,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 
				dc_retain_state(old_dm_state->context);

		}

	}

	/* Perform validation of MST topology in the state*/

	ret = drm_dp_mst_atomic_check(state);

	if (ret)

		goto fail;



	/* Store the overall update type for use later in atomic check. */

	for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+1 −0
Original line number Diff line number Diff line
@@ -330,6 +330,7 @@ struct amdgpu_dm_connector { 
	struct drm_dp_mst_port *port;

	struct amdgpu_dm_connector *mst_port;

	struct amdgpu_encoder *mst_encoder;

	struct drm_dp_aux *dsc_aux;



	/* TODO see if we can merge with ddc_bus or make a dm_connector */

	struct amdgpu_i2c_adapter *i2c;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+18 −1
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#include "dc.h"

#include "amdgpu_dm.h"

#include "amdgpu_dm_irq.h"

#include "amdgpu_dm_mst_types.h"



#include "dm_helpers.h"
@@ -516,8 +517,24 @@ bool dm_helpers_dp_write_dsc_enable( 
)

{

	uint8_t enable_dsc = enable ? 1 : 0;

	struct amdgpu_dm_connector *aconnector;



	if (!stream)

		return false;



	return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);

	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

		aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;



		if (!aconnector->dsc_aux)

			return false;



		return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0);

	}



	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)

		return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);



	return false;

}



bool dm_helpers_is_dp_sink_present(struct dc_link *link)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+419 −1
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include <linux/version.h>

#include <drm/drm_atomic_helper.h>

#include <drm/drm_dp_mst_helper.h>

#include "dm_services.h"

#include "amdgpu.h"

#include "amdgpu_dm.h"
@@ -39,6 +40,12 @@ 
#if defined(CONFIG_DEBUG_FS)

#include "amdgpu_dm_debugfs.h"

#endif





#if defined(CONFIG_DRM_AMD_DC_DCN)

#include "dc/dcn20/dcn20_resource.h"

#endif



/* #define TRACE_DPCD */



#ifdef TRACE_DPCD
@@ -180,6 +187,30 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { 
	.early_unregister = amdgpu_dm_mst_connector_early_unregister,

};



#if defined(CONFIG_DRM_AMD_DC_DCN)

static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)

{

	struct dc_sink *dc_sink = aconnector->dc_sink;

	struct drm_dp_mst_port *port = aconnector->port;

	u8 dsc_caps[16] = { 0 };



	aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);



	if (!aconnector->dsc_aux)

		return false;



	if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)

		return false;



	if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,

				   dsc_caps, NULL,

				   &dc_sink->sink_dsc_caps.dsc_dec_caps))

		return false;



	return true;

}

#endif



static int dm_dp_mst_get_modes(struct drm_connector *connector)

{

	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
@@ -222,10 +253,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) 
		/* dc_link_add_remote_sink returns a new reference */

		aconnector->dc_sink = dc_sink;



		if (aconnector->dc_sink)

		if (aconnector->dc_sink) {

			amdgpu_dm_update_freesync_caps(

					connector, aconnector->edid);



#if defined(CONFIG_DRM_AMD_DC_DCN)

			if (!validate_dsc_caps_on_connector(aconnector))

				memset(&aconnector->dc_sink->sink_dsc_caps,

				       0, sizeof(aconnector->dc_sink->sink_dsc_caps));

#endif

		}

	}



	drm_connector_update_edid_property(
@@ -466,3 +503,384 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 
		aconnector->connector_id);

}



int dm_mst_get_pbn_divider(struct dc_link *link)

{

	if (!link)

		return 0;



	return dc_link_bandwidth_kbps(link,

			dc_link_get_link_cap(link)) / (8 * 1000 * 54);

}



#if defined(CONFIG_DRM_AMD_DC_DCN)



struct dsc_mst_fairness_params {

	struct dc_crtc_timing *timing;

	struct dc_sink *sink;

	struct dc_dsc_bw_range bw_range;

	bool compression_possible;

	struct drm_dp_mst_port *port;

};



struct dsc_mst_fairness_vars {

	int pbn;

	bool dsc_enabled;

	int bpp_x16;

};



static int kbps_to_peak_pbn(int kbps)

{

	u64 peak_kbps = kbps;



	peak_kbps *= 1006;

	peak_kbps = div_u64(peak_kbps, 1000);

	return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));

}



static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,

		struct dsc_mst_fairness_vars *vars,

		int count)

{

	int i;



	for (i = 0; i < count; i++) {

		memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));

		if (vars[i].dsc_enabled && dc_dsc_compute_config(

					params[i].sink->ctx->dc->res_pool->dscs[0],

					&params[i].sink->sink_dsc_caps.dsc_dec_caps,

					params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,

					0,

					params[i].timing,

					&params[i].timing->dsc_cfg)) {

			params[i].timing->flags.DSC = 1;

			params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;

		} else {

			params[i].timing->flags.DSC = 0;

		}

	}

}



static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)

{

	struct dc_dsc_config dsc_config;

	u64 kbps;



	kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);

	dc_dsc_compute_config(

			param.sink->ctx->dc->res_pool->dscs[0],

			&param.sink->sink_dsc_caps.dsc_dec_caps,

			param.sink->ctx->dc->debug.dsc_min_slice_height_override,

			(int) kbps, param.timing, &dsc_config);



	return dsc_config.bits_per_pixel;

}



static void increase_dsc_bpp(struct drm_atomic_state *state,

			     struct dc_link *dc_link,

			     struct dsc_mst_fairness_params *params,

			     struct dsc_mst_fairness_vars *vars,

			     int count)

{

	int i;

	bool bpp_increased[MAX_PIPES];

	int initial_slack[MAX_PIPES];

	int min_initial_slack;

	int next_index;

	int remaining_to_increase = 0;

	int pbn_per_timeslot;

	int link_timeslots_used;

	int fair_pbn_alloc;



	for (i = 0; i < count; i++) {

		if (vars[i].dsc_enabled) {

			initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;

			bpp_increased[i] = false;

			remaining_to_increase += 1;

		} else {

			initial_slack[i] = 0;

			bpp_increased[i] = true;

		}

	}



	pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,

			dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);



	while (remaining_to_increase) {

		next_index = -1;

		min_initial_slack = -1;

		for (i = 0; i < count; i++) {

			if (!bpp_increased[i]) {

				if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {

					min_initial_slack = initial_slack[i];

					next_index = i;

				}

			}

		}



		if (next_index == -1)

			break;



		link_timeslots_used = 0;



		for (i = 0; i < count; i++)

			link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);



		fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;



		if (initial_slack[next_index] > fair_pbn_alloc) {

			vars[next_index].pbn += fair_pbn_alloc;

			if (drm_dp_atomic_find_vcpi_slots(state,

							  params[next_index].port->mgr,

							  params[next_index].port,

							  vars[next_index].pbn,\

							  dm_mst_get_pbn_divider(dc_link)) < 0)

				return;

			if (!drm_dp_mst_atomic_check(state)) {

				vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);

			} else {

				vars[next_index].pbn -= fair_pbn_alloc;

				if (drm_dp_atomic_find_vcpi_slots(state,

								  params[next_index].port->mgr,

								  params[next_index].port,

								  vars[next_index].pbn,

								  dm_mst_get_pbn_divider(dc_link)) < 0)

					return;

			}

		} else {

			vars[next_index].pbn += initial_slack[next_index];

			if (drm_dp_atomic_find_vcpi_slots(state,

							  params[next_index].port->mgr,

							  params[next_index].port,

							  vars[next_index].pbn,

							  dm_mst_get_pbn_divider(dc_link)) < 0)

				return;

			if (!drm_dp_mst_atomic_check(state)) {

				vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;

			} else {

				vars[next_index].pbn -= initial_slack[next_index];

				if (drm_dp_atomic_find_vcpi_slots(state,

								  params[next_index].port->mgr,

								  params[next_index].port,

								  vars[next_index].pbn,

								  dm_mst_get_pbn_divider(dc_link)) < 0)

					return;

			}

		}



		bpp_increased[next_index] = true;

		remaining_to_increase--;

	}

}



static void try_disable_dsc(struct drm_atomic_state *state,

			    struct dc_link *dc_link,

			    struct dsc_mst_fairness_params *params,

			    struct dsc_mst_fairness_vars *vars,

			    int count)

{

	int i;

	bool tried[MAX_PIPES];

	int kbps_increase[MAX_PIPES];

	int max_kbps_increase;

	int next_index;

	int remaining_to_try = 0;



	for (i = 0; i < count; i++) {

		if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {

			kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;

			tried[i] = false;

			remaining_to_try += 1;

		} else {

			kbps_increase[i] = 0;

			tried[i] = true;

		}

	}



	while (remaining_to_try) {

		next_index = -1;

		max_kbps_increase = -1;

		for (i = 0; i < count; i++) {

			if (!tried[i]) {

				if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {

					max_kbps_increase = kbps_increase[i];

					next_index = i;

				}

			}

		}



		if (next_index == -1)

			break;



		vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);

		if (drm_dp_atomic_find_vcpi_slots(state,

						  params[next_index].port->mgr,

						  params[next_index].port,

						  vars[next_index].pbn,

						  0) < 0)

			return;



		if (!drm_dp_mst_atomic_check(state)) {

			vars[next_index].dsc_enabled = false;

			vars[next_index].bpp_x16 = 0;

		} else {

			vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);

			if (drm_dp_atomic_find_vcpi_slots(state,

							  params[next_index].port->mgr,

							  params[next_index].port,

							  vars[next_index].pbn,

							  dm_mst_get_pbn_divider(dc_link)) < 0)

				return;

		}



		tried[next_index] = true;

		remaining_to_try--;

	}

}



static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,

					     struct dc_state *dc_state,

					     struct dc_link *dc_link)

{

	int i;

	struct dc_stream_state *stream;

	struct dsc_mst_fairness_params params[MAX_PIPES];

	struct dsc_mst_fairness_vars vars[MAX_PIPES];

	struct amdgpu_dm_connector *aconnector;

	int count = 0;



	memset(params, 0, sizeof(params));



	/* Set up params */

	for (i = 0; i < dc_state->stream_count; i++) {

		struct dc_dsc_policy dsc_policy = {0};



		stream = dc_state->streams[i];



		if (stream->link != dc_link)

			continue;



		stream->timing.flags.DSC = 0;



		params[count].timing = &stream->timing;

		params[count].sink = stream->sink;

		aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;

		params[count].port = aconnector->port;

		params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported;

		dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);

		if (!dc_dsc_compute_bandwidth_range(

				stream->sink->ctx->dc->res_pool->dscs[0],

				stream->sink->ctx->dc->debug.dsc_min_slice_height_override,

				dsc_policy.min_target_bpp,

				dsc_policy.max_target_bpp,

				&stream->sink->sink_dsc_caps.dsc_dec_caps,

				&stream->timing, &params[count].bw_range))

			params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);



		count++;

	}

	/* Try no compression */

	for (i = 0; i < count; i++) {

		vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);

		vars[i].dsc_enabled = false;

		vars[i].bpp_x16 = 0;

		if (drm_dp_atomic_find_vcpi_slots(state,

						 params[i].port->mgr,

						 params[i].port,

						 vars[i].pbn,

						 0) < 0)

			return false;

	}

	if (!drm_dp_mst_atomic_check(state)) {

		set_dsc_configs_from_fairness_vars(params, vars, count);

		return true;

	}



	/* Try max compression */

	for (i = 0; i < count; i++) {

		if (params[i].compression_possible) {

			vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);

			vars[i].dsc_enabled = true;

			vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;

			if (drm_dp_atomic_find_vcpi_slots(state,

							  params[i].port->mgr,

							  params[i].port,

							  vars[i].pbn,

							  dm_mst_get_pbn_divider(dc_link)) < 0)

				return false;

		} else {

			vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);

			vars[i].dsc_enabled = false;

			vars[i].bpp_x16 = 0;

			if (drm_dp_atomic_find_vcpi_slots(state,

							  params[i].port->mgr,

							  params[i].port,

							  vars[i].pbn,

							  0) < 0)

				return false;

		}

	}

	if (drm_dp_mst_atomic_check(state))

		return false;



	/* Optimize degree of compression */

	increase_dsc_bpp(state, dc_link, params, vars, count);



	try_disable_dsc(state, dc_link, params, vars, count);



	set_dsc_configs_from_fairness_vars(params, vars, count);



	return true;

}



bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,

				       struct dc_state *dc_state)

{

	int i, j;

	struct dc_stream_state *stream;

	bool computed_streams[MAX_PIPES];

	struct amdgpu_dm_connector *aconnector;



	for (i = 0; i < dc_state->stream_count; i++)

		computed_streams[i] = false;



	for (i = 0; i < dc_state->stream_count; i++) {

		stream = dc_state->streams[i];



		if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)

			continue;



		aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;



		if (!aconnector || !aconnector->dc_sink)

			continue;



		if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)

			continue;



		if (computed_streams[i])

			continue;



		mutex_lock(&aconnector->mst_mgr.lock);

		if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {

			mutex_unlock(&aconnector->mst_mgr.lock);

			return false;

		}

		mutex_unlock(&aconnector->mst_mgr.lock);



		for (j = 0; j < dc_state->stream_count; j++) {

			if (dc_state->streams[j]->link == stream->link)

				computed_streams[j] = true;

		}

	}



	for (i = 0; i < dc_state->stream_count; i++) {

		stream = dc_state->streams[i];



		if (stream->timing.flags.DSC == 1)

			dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);

	}



	return true;

}



#endif

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h

+7 −0
Original line number Diff line number Diff line
@@ -29,7 +29,14 @@ 
struct amdgpu_display_manager;

struct amdgpu_dm_connector;



int dm_mst_get_pbn_divider(struct dc_link *link);



void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,

				       struct amdgpu_dm_connector *aconnector);



#if defined(CONFIG_DRM_AMD_DC_DCN)

bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,

				       struct dc_state *dc_state);

#endif



#endif

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