Commit 6861c837 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/si/dpm: fix symbol conflicts with radeon 



Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarEdward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a1047777

drivers/gpu/drm/amd/amdgpu/si_dpm.c

+147 −140
Original line number Diff line number Diff line
@@ -2274,7 +2274,7 @@ static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, 
		smc_table->dpm2Params.SafePowerLimit =

			cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);



		ret = si_copy_bytes_to_smc(adev,

		ret = amdgpu_si_copy_bytes_to_smc(adev,

						  (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +

						   offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),

						  (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
@@ -2293,7 +2293,7 @@ static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, 
			papm_parm->PlatformPowerLimit = 0xffffffff;

			papm_parm->NearTDPLimitPAPM = 0xffffffff;



			ret = si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,

			ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,

							  (u8 *)papm_parm,

							  sizeof(PP_SIslands_PAPMParameters),

							  si_pi->sram_end);
@@ -2322,7 +2322,7 @@ static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, 
		smc_table->dpm2Params.SafePowerLimit =

			cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);



		ret = si_copy_bytes_to_smc(adev,

		ret = amdgpu_si_copy_bytes_to_smc(adev,

						  (si_pi->state_table_start +

						   offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +

						   offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
@@ -2538,7 +2538,7 @@ static int si_enable_power_containment(struct amdgpu_device *adev, 
	if (ni_pi->enable_power_containment) {

		if (enable) {

			if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {

				smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);

				smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);

				if (smc_result != PPSMC_Result_OK) {

					ret = -EINVAL;

					ni_pi->pc_enabled = false;
@@ -2547,7 +2547,7 @@ static int si_enable_power_containment(struct amdgpu_device *adev, 
				}

			}

		} else {

			smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);

			smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);

			if (smc_result != PPSMC_Result_OK)

				ret = -EINVAL;

			ni_pi->pc_enabled = false;
@@ -2615,8 +2615,10 @@ static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) 
		dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);

	}



	ret = si_copy_bytes_to_smc(adev, si_pi->dte_table_start, (u8 *)dte_tables,

				   sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);

	ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,

					  (u8 *)dte_tables,

					  sizeof(Smc_SIslands_DTE_Configuration),

					  si_pi->sram_end);

	kfree(dte_tables);



	return ret;
@@ -2806,8 +2808,10 @@ static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) 
	cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);

	cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);



	ret = si_copy_bytes_to_smc(adev, si_pi->cac_table_start, (u8 *)cac_tables,

				   sizeof(PP_SIslands_CacConfig), si_pi->sram_end);

	ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,

					  (u8 *)cac_tables,

					  sizeof(PP_SIslands_CacConfig),

					  si_pi->sram_end);



	if (ret)

		goto done_free;
@@ -2900,12 +2904,12 @@ static int si_enable_smc_cac(struct amdgpu_device *adev, 
		if (enable) {

			if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {

				if (ni_pi->support_cac_long_term_average) {

					smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);

					smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);

					if (smc_result != PPSMC_Result_OK)

						ni_pi->support_cac_long_term_average = false;

				}



				smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);

				smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);

				if (smc_result != PPSMC_Result_OK) {

					ret = -EINVAL;

					ni_pi->cac_enabled = false;
@@ -2914,21 +2918,21 @@ static int si_enable_smc_cac(struct amdgpu_device *adev, 
				}



				if (si_pi->enable_dte) {

					smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);

					smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);

					if (smc_result != PPSMC_Result_OK)

						ret = -EINVAL;

				}

			}

		} else if (ni_pi->cac_enabled) {

			if (si_pi->enable_dte)

				smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);

				smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);



			smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);

			smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);



			ni_pi->cac_enabled = false;



			if (ni_pi->support_cac_long_term_average)

				smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);

				smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);

		}

	}

	return ret;
@@ -2992,8 +2996,9 @@ static int si_init_smc_spll_table(struct amdgpu_device *adev) 




	if (!ret)

		ret = si_copy_bytes_to_smc(adev, si_pi->spll_table_start,

					   (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),

		ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,

						  (u8 *)spll_table,

						  sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),

						  si_pi->sram_end);



	if (ret)
@@ -3664,7 +3669,7 @@ static int si_read_smc_soft_register(struct amdgpu_device *adev, 
{

	struct si_power_info *si_pi = si_get_pi(adev);



	return si_read_smc_sram_dword(adev,

	return amdgpu_si_read_smc_sram_dword(adev,

					     si_pi->soft_regs_start + reg_offset, value,

					     si_pi->sram_end);

}
@@ -3675,7 +3680,7 @@ static int si_write_smc_soft_register(struct amdgpu_device *adev, 
{

	struct si_power_info *si_pi = si_get_pi(adev);



	return si_write_smc_sram_dword(adev,

	return amdgpu_si_write_smc_sram_dword(adev,

					      si_pi->soft_regs_start + reg_offset,

					      value, si_pi->sram_end);

}
@@ -3834,7 +3839,7 @@ static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, 
	PPSMC_Result ret;



	if (thermal_level == 0) {

		ret = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);

		ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);

		if (ret == PPSMC_Result_OK)

			return 0;

		else
@@ -3853,7 +3858,7 @@ static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) 
static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)

{

	if (ac_power)

		return (si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?

		return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?

			0 : -EINVAL;



	return 0;
@@ -3864,12 +3869,12 @@ static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev 
						      PPSMC_Msg msg, u32 parameter)

{

	WREG32(SMC_SCRATCH0, parameter);

	return si_send_msg_to_smc(adev, msg);

	return amdgpu_si_send_msg_to_smc(adev, msg);

}



static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)

{

	if (si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)

	if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)

		return -EINVAL;



	return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
@@ -3911,46 +3916,46 @@ static int si_dpm_force_performance_level(struct amdgpu_device *adev, 
#if 0

static int si_set_boot_state(struct amdgpu_device *adev)

{

	return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?

	return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?

		0 : -EINVAL;

}

#endif



static int si_set_sw_state(struct amdgpu_device *adev)

{

	return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?

	return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?

		0 : -EINVAL;

}



static int si_halt_smc(struct amdgpu_device *adev)

{

	if (si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)

	if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)

		return -EINVAL;



	return (si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?

	return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?

		0 : -EINVAL;

}



static int si_resume_smc(struct amdgpu_device *adev)

{

	if (si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)

	if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)

		return -EINVAL;



	return (si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?

	return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?

		0 : -EINVAL;

}



static void si_dpm_start_smc(struct amdgpu_device *adev)

{

	si_program_jump_on_start(adev);

	si_start_smc(adev);

	si_smc_clock(adev, true);

	amdgpu_si_program_jump_on_start(adev);

	amdgpu_si_start_smc(adev);

	amdgpu_si_smc_clock(adev, true);

}



static void si_dpm_stop_smc(struct amdgpu_device *adev)

{

	si_reset_smc(adev);

	si_smc_clock(adev, false);

	amdgpu_si_reset_smc(adev);

	amdgpu_si_smc_clock(adev, false);

}



static int si_process_firmware_header(struct amdgpu_device *adev)
@@ -3959,7 +3964,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 
	u32 tmp;

	int ret;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_stateTable,

					    &tmp, si_pi->sram_end);
@@ -3968,7 +3973,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 


	si_pi->state_table_start = tmp;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,

					    &tmp, si_pi->sram_end);
@@ -3977,7 +3982,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 


	si_pi->soft_regs_start = tmp;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,

					    &tmp, si_pi->sram_end);
@@ -3986,7 +3991,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 


	si_pi->mc_reg_table_start = tmp;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_fanTable,

					    &tmp, si_pi->sram_end);
@@ -3995,7 +4000,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 


	si_pi->fan_table_start = tmp;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,

					    &tmp, si_pi->sram_end);
@@ -4004,7 +4009,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 


	si_pi->arb_table_start = tmp;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,

					    &tmp, si_pi->sram_end);
@@ -4013,7 +4018,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 


	si_pi->cac_table_start = tmp;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,

					    &tmp, si_pi->sram_end);
@@ -4022,7 +4027,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 


	si_pi->dte_table_start = tmp;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_spllTable,

					    &tmp, si_pi->sram_end);
@@ -4031,7 +4036,7 @@ static int si_process_firmware_header(struct amdgpu_device *adev) 


	si_pi->spll_table_start = tmp;



	ret = si_read_smc_sram_dword(adev,

	ret = amdgpu_si_read_smc_sram_dword(adev,

					    SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +

					    SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,

					    &tmp, si_pi->sram_end);
@@ -4112,7 +4117,7 @@ static int si_notify_smc_display_change(struct amdgpu_device *adev, 
	PPSMC_Msg msg = has_display ?

		PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;



	return (si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?

	return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?

		0 : -EINVAL;

}
@@ -4365,10 +4370,10 @@ static int si_upload_firmware(struct amdgpu_device *adev) 
{

	struct si_power_info *si_pi = si_get_pi(adev);



	si_reset_smc(adev);

	si_smc_clock(adev, false);

	amdgpu_si_reset_smc(adev);

	amdgpu_si_smc_clock(adev, false);



	return si_load_smc_ucode(adev, si_pi->sram_end);

	return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);

}



static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
@@ -4712,14 +4717,16 @@ static int si_init_arb_table_index(struct amdgpu_device *adev) 
	u32 tmp;

	int ret;



	ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start, &tmp, si_pi->sram_end);

	ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,

					    &tmp, si_pi->sram_end);

	if (ret)

		return ret;



	tmp &= 0x00FFFFFF;

	tmp |= MC_CG_ARB_FREQ_F1 << 24;



	return si_write_smc_sram_dword(adev, si_pi->arb_table_start,  tmp, si_pi->sram_end);

	return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,

					      tmp, si_pi->sram_end);

}



static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
@@ -4729,7 +4736,7 @@ static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) 


static int si_reset_to_default(struct amdgpu_device *adev)

{

	return (si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?

	return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?

		0 : -EINVAL;

}
@@ -4739,7 +4746,7 @@ static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) 
	u32 tmp;

	int ret;



	ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start,

	ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,

					    &tmp, si_pi->sram_end);

	if (ret)

		return ret;
@@ -4810,7 +4817,7 @@ static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, 
		ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);

		if (ret)

			break;

		ret = si_copy_bytes_to_smc(adev,

		ret = amdgpu_si_copy_bytes_to_smc(adev,

						  si_pi->arb_table_start +

						  offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +

						  sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
@@ -5152,7 +5159,7 @@ static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) 
	si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,

				   ulv->volt_change_delay);



	ret = si_copy_bytes_to_smc(adev,

	ret = amdgpu_si_copy_bytes_to_smc(adev,

					  si_pi->arb_table_start +

					  offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +

					  sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
@@ -5252,7 +5259,7 @@ static int si_init_smc_table(struct amdgpu_device *adev) 
		table->ULVState = table->initialState;

	}



	return si_copy_bytes_to_smc(adev, si_pi->state_table_start,

	return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,

					   (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),

					   si_pi->sram_end);

}
@@ -5616,7 +5623,7 @@ static int si_disable_ulv(struct amdgpu_device *adev) 
	struct si_ulv_param *ulv = &si_pi->ulv;



	if (ulv->supported)

		return (si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?

		return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?

			0 : -EINVAL;



	return 0;
@@ -5658,7 +5665,7 @@ static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *ade 


	if (ulv->supported) {

		if (si_is_state_ulv_compatible(adev, amdgpu_new_state))

			return (si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?

			return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?

				0 : -EINVAL;

	}

	return 0;
@@ -5763,7 +5770,7 @@ static int si_upload_sw_state(struct amdgpu_device *adev, 
	if (ret)

		return ret;



	return si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,

	return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,

					   state_size, si_pi->sram_end);

}
@@ -5783,7 +5790,7 @@ static int si_upload_ulv_state(struct amdgpu_device *adev) 


		ret = si_populate_ulv_state(adev, smc_state);

		if (!ret)

			ret = si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,

			ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,

							  state_size, si_pi->sram_end);

	}
@@ -6155,7 +6162,7 @@ static int si_populate_mc_reg_table(struct amdgpu_device *adev, 


	si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);



	return si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,

	return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,

					   (u8 *)smc_mc_reg_table,

					   sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);

}
@@ -6174,7 +6181,7 @@ static int si_upload_mc_reg_table(struct amdgpu_device *adev, 


	si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);



	return si_copy_bytes_to_smc(adev, address,

	return amdgpu_si_copy_bytes_to_smc(adev, address,

					   (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],

					   sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,

					   si_pi->sram_end);
@@ -6285,11 +6292,11 @@ static int si_ds_request(struct amdgpu_device *adev, 


	if (eg_pi->sclk_deep_sleep) {

		if (ds_status_on)

			return (si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==

			return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==

				PPSMC_Result_OK) ?

				0 : -EINVAL;

		else

			return (si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==

			return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==

				PPSMC_Result_OK) ? 0 : -EINVAL;

	}

	return 0;
@@ -6420,7 +6427,7 @@ static int si_thermal_enable_alert(struct amdgpu_device *adev, 


		thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);

		WREG32(CG_THERMAL_INT, thermal_int);

		result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);

		result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);

		if (result != PPSMC_Result_OK) {

			DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");

			return -EINVAL;
@@ -6535,7 +6542,7 @@ static int si_thermal_setup_fan_table(struct amdgpu_device *adev) 
	tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;

	fan_table.temp_src = (uint8_t)tmp;



	ret = si_copy_bytes_to_smc(adev,

	ret = amdgpu_si_copy_bytes_to_smc(adev,

					  si_pi->fan_table_start,

					  (u8 *)(&fan_table),

					  sizeof(fan_table),
@@ -6554,7 +6561,7 @@ static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) 
	struct si_power_info *si_pi = si_get_pi(adev);

	PPSMC_Result ret;



	ret = si_send_msg_to_smc(adev, PPSMC_StartFanControl);

	ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);

	if (ret == PPSMC_Result_OK) {

		si_pi->fan_is_controlled_by_smc = true;

		return 0;
@@ -6568,7 +6575,7 @@ static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) 
	struct si_power_info *si_pi = si_get_pi(adev);

	PPSMC_Result ret;



	ret = si_send_msg_to_smc(adev, PPSMC_StopFanControl);

	ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);



	if (ret == PPSMC_Result_OK) {

		si_pi->fan_is_controlled_by_smc = false;
@@ -6799,7 +6806,7 @@ static int si_dpm_enable(struct amdgpu_device *adev) 
	struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;

	int ret;



	if (si_is_smc_running(adev))

	if (amdgpu_si_is_smc_running(adev))

		return -EINVAL;

	if (pi->voltage_control || si_pi->voltage_control_svi2)

		si_enable_voltage_control(adev, true);
@@ -6930,7 +6937,7 @@ static void si_dpm_disable(struct amdgpu_device *adev) 
	struct rv7xx_power_info *pi = rv770_get_pi(adev);

	struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;



	if (!si_is_smc_running(adev))

	if (!amdgpu_si_is_smc_running(adev))

		return;

	si_thermal_stop_thermal_controller(adev);

	si_disable_ulv(adev);

drivers/gpu/drm/amd/amdgpu/si_smc.c

+19 −18
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ static int si_set_smc_sram_address(struct amdgpu_device *adev, 
	return 0;

}



int si_copy_bytes_to_smc(struct amdgpu_device *adev,

int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,

				u32 smc_start_address,

				const u8 *src, u32 byte_count, u32 limit)

{
@@ -108,7 +108,7 @@ done: 
	return ret;

}



void si_start_smc(struct amdgpu_device *adev)

void amdgpu_si_start_smc(struct amdgpu_device *adev)

{

	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
@@ -117,7 +117,7 @@ void si_start_smc(struct amdgpu_device *adev) 
	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);

}



void si_reset_smc(struct amdgpu_device *adev)

void amdgpu_si_reset_smc(struct amdgpu_device *adev)

{

	u32 tmp;
@@ -131,14 +131,14 @@ void si_reset_smc(struct amdgpu_device *adev) 
	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);

}



int si_program_jump_on_start(struct amdgpu_device *adev)

int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev)

{

	static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };



	return si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);

	return amdgpu_si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);

}



void si_smc_clock(struct amdgpu_device *adev, bool enable)

void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable)

{

	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
@@ -150,7 +150,7 @@ void si_smc_clock(struct amdgpu_device *adev, bool enable) 
	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);

}



bool si_is_smc_running(struct amdgpu_device *adev)

bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)

{

	u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
@@ -161,12 +161,13 @@ bool si_is_smc_running(struct amdgpu_device *adev) 
	return false;

}



PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)

PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev,

				       PPSMC_Msg msg)

{

	u32 tmp;

	int i;



	if (!si_is_smc_running(adev))

	if (!amdgpu_si_is_smc_running(adev))

		return PPSMC_Result_Failed;



	WREG32(SMC_MESSAGE_0, msg);
@@ -181,12 +182,12 @@ PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg) 
	return (PPSMC_Result)RREG32(SMC_RESP_0);

}



PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev)

PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev)

{

	u32 tmp;

	int i;



	if (!si_is_smc_running(adev))

	if (!amdgpu_si_is_smc_running(adev))

		return PPSMC_Result_OK;



	for (i = 0; i < adev->usec_timeout; i++) {
@@ -199,7 +200,7 @@ PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev) 
	return PPSMC_Result_OK;

}



int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)

int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)

{

	const struct smc_firmware_header_v1_0 *hdr;

	unsigned long flags;
@@ -241,7 +242,7 @@ int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) 
	return 0;

}



int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

				  u32 *value, u32 limit)

{

	unsigned long flags;
@@ -256,7 +257,7 @@ int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 
	return ret;

}



int si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

				   u32 value, u32 limit)

{

	unsigned long flags;

drivers/gpu/drm/amd/amdgpu/sislands_smc.h

+15 −15
Original line number Diff line number Diff line
@@ -402,20 +402,20 @@ typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration; 


#pragma pack(pop)



int si_copy_bytes_to_smc(struct amdgpu_device *adev,

int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,

				u32 smc_start_address,

				const u8 *src, u32 byte_count, u32 limit);

void si_start_smc(struct amdgpu_device *adev);

void si_reset_smc(struct amdgpu_device *adev);

int si_program_jump_on_start(struct amdgpu_device *adev);

void si_smc_clock(struct amdgpu_device *adev, bool enable);

bool si_is_smc_running(struct amdgpu_device *adev);

PPSMC_Result si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);

PPSMC_Result si_wait_for_smc_inactive(struct amdgpu_device *adev);

int si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);

int si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

void amdgpu_si_start_smc(struct amdgpu_device *adev);

void amdgpu_si_reset_smc(struct amdgpu_device *adev);

int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev);

void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable);

bool amdgpu_si_is_smc_running(struct amdgpu_device *adev);

PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);

PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev);

int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);

int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

				  u32 *value, u32 limit);

int si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,

				   u32 value, u32 limit);



#endif

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