Commit 68608b5e authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Santosh Shilimkar
Browse files

firmware: ti_sci: Add resource management APIs for ringacc, psi-l and udma 



Configuration of NAVSS resource, like rings, UDMAP channels, flows
and PSI-L thread management need to be done via TISCI.

Add the needed structures and functions for NAVSS resource configuration of
the following:
Rings from Ring Accelerator
PSI-L thread management
UDMAP tchan, rchan and rflow configuration.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@oracle.com>
parent 66f030ea

drivers/firmware/ti_sci.c

+488 −0
Original line number Diff line number Diff line
@@ -2004,6 +2004,481 @@ static int ti_sci_cmd_free_event_map(const struct ti_sci_handle *handle, 
			       ia_id, vint, global_event, vint_status_bit, 0);

}



/**

 * ti_sci_cmd_ring_config() - configure RA ring

 * @handle:		Pointer to TI SCI handle.

 * @valid_params:	Bitfield defining validity of ring configuration

 *			parameters

 * @nav_id:		Device ID of Navigator Subsystem from which the ring is

 *			allocated

 * @index:		Ring index

 * @addr_lo:		The ring base address lo 32 bits

 * @addr_hi:		The ring base address hi 32 bits

 * @count:		Number of ring elements

 * @mode:		The mode of the ring

 * @size:		The ring element size.

 * @order_id:		Specifies the ring's bus order ID

 *

 * Return: 0 if all went well, else returns appropriate error value.

 *

 * See @ti_sci_msg_rm_ring_cfg_req for more info.

 */

static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle,

				  u32 valid_params, u16 nav_id, u16 index,

				  u32 addr_lo, u32 addr_hi, u32 count,

				  u8 mode, u8 size, u8 order_id)

{

	struct ti_sci_msg_rm_ring_cfg_req *req;

	struct ti_sci_msg_hdr *resp;

	struct ti_sci_xfer *xfer;

	struct ti_sci_info *info;

	struct device *dev;

	int ret = 0;



	if (IS_ERR_OR_NULL(handle))

		return -EINVAL;



	info = handle_to_ti_sci_info(handle);

	dev = info->dev;



	xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_CFG,

				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,

				   sizeof(*req), sizeof(*resp));

	if (IS_ERR(xfer)) {

		ret = PTR_ERR(xfer);

		dev_err(info->dev, "RM_RA:Message config failed(%d)\n", ret);

		return ret;

	}

	req = (struct ti_sci_msg_rm_ring_cfg_req *)xfer->xfer_buf;

	req->valid_params = valid_params;

	req->nav_id = nav_id;

	req->index = index;

	req->addr_lo = addr_lo;

	req->addr_hi = addr_hi;

	req->count = count;

	req->mode = mode;

	req->size = size;

	req->order_id = order_id;



	ret = ti_sci_do_xfer(info, xfer);

	if (ret) {

		dev_err(info->dev, "RM_RA:Mbox config send fail %d\n", ret);

		goto fail;

	}



	resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;

	ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV;



fail:

	ti_sci_put_one_xfer(&info->minfo, xfer);

	dev_dbg(info->dev, "RM_RA:config ring %u ret:%d\n", index, ret);

	return ret;

}



/**

 * ti_sci_cmd_ring_get_config() - get RA ring configuration

 * @handle:	Pointer to TI SCI handle.

 * @nav_id:	Device ID of Navigator Subsystem from which the ring is

 *		allocated

 * @index:	Ring index

 * @addr_lo:	Returns ring's base address lo 32 bits

 * @addr_hi:	Returns ring's base address hi 32 bits

 * @count:	Returns number of ring elements

 * @mode:	Returns mode of the ring

 * @size:	Returns ring element size

 * @order_id:	Returns ring's bus order ID

 *

 * Return: 0 if all went well, else returns appropriate error value.

 *

 * See @ti_sci_msg_rm_ring_get_cfg_req for more info.

 */

static int ti_sci_cmd_ring_get_config(const struct ti_sci_handle *handle,

				      u32 nav_id, u32 index, u8 *mode,

				      u32 *addr_lo, u32 *addr_hi,

				      u32 *count, u8 *size, u8 *order_id)

{

	struct ti_sci_msg_rm_ring_get_cfg_resp *resp;

	struct ti_sci_msg_rm_ring_get_cfg_req *req;

	struct ti_sci_xfer *xfer;

	struct ti_sci_info *info;

	struct device *dev;

	int ret = 0;



	if (IS_ERR_OR_NULL(handle))

		return -EINVAL;



	info = handle_to_ti_sci_info(handle);

	dev = info->dev;



	xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_GET_CFG,

				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,

				   sizeof(*req), sizeof(*resp));

	if (IS_ERR(xfer)) {

		ret = PTR_ERR(xfer);

		dev_err(info->dev,

			"RM_RA:Message get config failed(%d)\n", ret);

		return ret;

	}

	req = (struct ti_sci_msg_rm_ring_get_cfg_req *)xfer->xfer_buf;

	req->nav_id = nav_id;

	req->index = index;



	ret = ti_sci_do_xfer(info, xfer);

	if (ret) {

		dev_err(info->dev, "RM_RA:Mbox get config send fail %d\n", ret);

		goto fail;

	}



	resp = (struct ti_sci_msg_rm_ring_get_cfg_resp *)xfer->xfer_buf;



	if (!ti_sci_is_response_ack(resp)) {

		ret = -ENODEV;

	} else {

		if (mode)

			*mode = resp->mode;

		if (addr_lo)

			*addr_lo = resp->addr_lo;

		if (addr_hi)

			*addr_hi = resp->addr_hi;

		if (count)

			*count = resp->count;

		if (size)

			*size = resp->size;

		if (order_id)

			*order_id = resp->order_id;

	};



fail:

	ti_sci_put_one_xfer(&info->minfo, xfer);

	dev_dbg(info->dev, "RM_RA:get config ring %u ret:%d\n", index, ret);

	return ret;

}



/**

 * ti_sci_cmd_rm_psil_pair() - Pair PSI-L source to destination thread

 * @handle:	Pointer to TI SCI handle.

 * @nav_id:	Device ID of Navigator Subsystem which should be used for

 *		pairing

 * @src_thread:	Source PSI-L thread ID

 * @dst_thread: Destination PSI-L thread ID

 *

 * Return: 0 if all went well, else returns appropriate error value.

 */

static int ti_sci_cmd_rm_psil_pair(const struct ti_sci_handle *handle,

				   u32 nav_id, u32 src_thread, u32 dst_thread)

{

	struct ti_sci_msg_psil_pair *req;

	struct ti_sci_msg_hdr *resp;

	struct ti_sci_xfer *xfer;

	struct ti_sci_info *info;

	struct device *dev;

	int ret = 0;



	if (IS_ERR(handle))

		return PTR_ERR(handle);

	if (!handle)

		return -EINVAL;



	info = handle_to_ti_sci_info(handle);

	dev = info->dev;



	xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_PSIL_PAIR,

				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,

				   sizeof(*req), sizeof(*resp));

	if (IS_ERR(xfer)) {

		ret = PTR_ERR(xfer);

		dev_err(dev, "RM_PSIL:Message reconfig failed(%d)\n", ret);

		return ret;

	}

	req = (struct ti_sci_msg_psil_pair *)xfer->xfer_buf;

	req->nav_id = nav_id;

	req->src_thread = src_thread;

	req->dst_thread = dst_thread;



	ret = ti_sci_do_xfer(info, xfer);

	if (ret) {

		dev_err(dev, "RM_PSIL:Mbox send fail %d\n", ret);

		goto fail;

	}



	resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;

	ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;



fail:

	ti_sci_put_one_xfer(&info->minfo, xfer);



	return ret;

}



/**

 * ti_sci_cmd_rm_psil_unpair() - Unpair PSI-L source from destination thread

 * @handle:	Pointer to TI SCI handle.

 * @nav_id:	Device ID of Navigator Subsystem which should be used for

 *		unpairing

 * @src_thread:	Source PSI-L thread ID

 * @dst_thread:	Destination PSI-L thread ID

 *

 * Return: 0 if all went well, else returns appropriate error value.

 */

static int ti_sci_cmd_rm_psil_unpair(const struct ti_sci_handle *handle,

				     u32 nav_id, u32 src_thread, u32 dst_thread)

{

	struct ti_sci_msg_psil_unpair *req;

	struct ti_sci_msg_hdr *resp;

	struct ti_sci_xfer *xfer;

	struct ti_sci_info *info;

	struct device *dev;

	int ret = 0;



	if (IS_ERR(handle))

		return PTR_ERR(handle);

	if (!handle)

		return -EINVAL;



	info = handle_to_ti_sci_info(handle);

	dev = info->dev;



	xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_PSIL_UNPAIR,

				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,

				   sizeof(*req), sizeof(*resp));

	if (IS_ERR(xfer)) {

		ret = PTR_ERR(xfer);

		dev_err(dev, "RM_PSIL:Message reconfig failed(%d)\n", ret);

		return ret;

	}

	req = (struct ti_sci_msg_psil_unpair *)xfer->xfer_buf;

	req->nav_id = nav_id;

	req->src_thread = src_thread;

	req->dst_thread = dst_thread;



	ret = ti_sci_do_xfer(info, xfer);

	if (ret) {

		dev_err(dev, "RM_PSIL:Mbox send fail %d\n", ret);

		goto fail;

	}



	resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;

	ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;



fail:

	ti_sci_put_one_xfer(&info->minfo, xfer);



	return ret;

}



/**

 * ti_sci_cmd_rm_udmap_tx_ch_cfg() - Configure a UDMAP TX channel

 * @handle:	Pointer to TI SCI handle.

 * @params:	Pointer to ti_sci_msg_rm_udmap_tx_ch_cfg TX channel config

 *		structure

 *

 * Return: 0 if all went well, else returns appropriate error value.

 *

 * See @ti_sci_msg_rm_udmap_tx_ch_cfg and @ti_sci_msg_rm_udmap_tx_ch_cfg_req for

 * more info.

 */

static int ti_sci_cmd_rm_udmap_tx_ch_cfg(const struct ti_sci_handle *handle,

			const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params)

{

	struct ti_sci_msg_rm_udmap_tx_ch_cfg_req *req;

	struct ti_sci_msg_hdr *resp;

	struct ti_sci_xfer *xfer;

	struct ti_sci_info *info;

	struct device *dev;

	int ret = 0;



	if (IS_ERR_OR_NULL(handle))

		return -EINVAL;



	info = handle_to_ti_sci_info(handle);

	dev = info->dev;



	xfer = ti_sci_get_one_xfer(info, TISCI_MSG_RM_UDMAP_TX_CH_CFG,

				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,

				   sizeof(*req), sizeof(*resp));

	if (IS_ERR(xfer)) {

		ret = PTR_ERR(xfer);

		dev_err(info->dev, "Message TX_CH_CFG alloc failed(%d)\n", ret);

		return ret;

	}

	req = (struct ti_sci_msg_rm_udmap_tx_ch_cfg_req *)xfer->xfer_buf;

	req->valid_params = params->valid_params;

	req->nav_id = params->nav_id;

	req->index = params->index;

	req->tx_pause_on_err = params->tx_pause_on_err;

	req->tx_filt_einfo = params->tx_filt_einfo;

	req->tx_filt_pswords = params->tx_filt_pswords;

	req->tx_atype = params->tx_atype;

	req->tx_chan_type = params->tx_chan_type;

	req->tx_supr_tdpkt = params->tx_supr_tdpkt;

	req->tx_fetch_size = params->tx_fetch_size;

	req->tx_credit_count = params->tx_credit_count;

	req->txcq_qnum = params->txcq_qnum;

	req->tx_priority = params->tx_priority;

	req->tx_qos = params->tx_qos;

	req->tx_orderid = params->tx_orderid;

	req->fdepth = params->fdepth;

	req->tx_sched_priority = params->tx_sched_priority;

	req->tx_burst_size = params->tx_burst_size;



	ret = ti_sci_do_xfer(info, xfer);

	if (ret) {

		dev_err(info->dev, "Mbox send TX_CH_CFG fail %d\n", ret);

		goto fail;

	}



	resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;

	ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;



fail:

	ti_sci_put_one_xfer(&info->minfo, xfer);

	dev_dbg(info->dev, "TX_CH_CFG: chn %u ret:%u\n", params->index, ret);

	return ret;

}



/**

 * ti_sci_cmd_rm_udmap_rx_ch_cfg() - Configure a UDMAP RX channel

 * @handle:	Pointer to TI SCI handle.

 * @params:	Pointer to ti_sci_msg_rm_udmap_rx_ch_cfg RX channel config

 *		structure

 *

 * Return: 0 if all went well, else returns appropriate error value.

 *

 * See @ti_sci_msg_rm_udmap_rx_ch_cfg and @ti_sci_msg_rm_udmap_rx_ch_cfg_req for

 * more info.

 */

static int ti_sci_cmd_rm_udmap_rx_ch_cfg(const struct ti_sci_handle *handle,

			const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params)

{

	struct ti_sci_msg_rm_udmap_rx_ch_cfg_req *req;

	struct ti_sci_msg_hdr *resp;

	struct ti_sci_xfer *xfer;

	struct ti_sci_info *info;

	struct device *dev;

	int ret = 0;



	if (IS_ERR_OR_NULL(handle))

		return -EINVAL;



	info = handle_to_ti_sci_info(handle);

	dev = info->dev;



	xfer = ti_sci_get_one_xfer(info, TISCI_MSG_RM_UDMAP_RX_CH_CFG,

				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,

				   sizeof(*req), sizeof(*resp));

	if (IS_ERR(xfer)) {

		ret = PTR_ERR(xfer);

		dev_err(info->dev, "Message RX_CH_CFG alloc failed(%d)\n", ret);

		return ret;

	}

	req = (struct ti_sci_msg_rm_udmap_rx_ch_cfg_req *)xfer->xfer_buf;

	req->valid_params = params->valid_params;

	req->nav_id = params->nav_id;

	req->index = params->index;

	req->rx_fetch_size = params->rx_fetch_size;

	req->rxcq_qnum = params->rxcq_qnum;

	req->rx_priority = params->rx_priority;

	req->rx_qos = params->rx_qos;

	req->rx_orderid = params->rx_orderid;

	req->rx_sched_priority = params->rx_sched_priority;

	req->flowid_start = params->flowid_start;

	req->flowid_cnt = params->flowid_cnt;

	req->rx_pause_on_err = params->rx_pause_on_err;

	req->rx_atype = params->rx_atype;

	req->rx_chan_type = params->rx_chan_type;

	req->rx_ignore_short = params->rx_ignore_short;

	req->rx_ignore_long = params->rx_ignore_long;

	req->rx_burst_size = params->rx_burst_size;



	ret = ti_sci_do_xfer(info, xfer);

	if (ret) {

		dev_err(info->dev, "Mbox send RX_CH_CFG fail %d\n", ret);

		goto fail;

	}



	resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;

	ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;



fail:

	ti_sci_put_one_xfer(&info->minfo, xfer);

	dev_dbg(info->dev, "RX_CH_CFG: chn %u ret:%d\n", params->index, ret);

	return ret;

}



/**

 * ti_sci_cmd_rm_udmap_rx_flow_cfg() - Configure UDMAP RX FLOW

 * @handle:	Pointer to TI SCI handle.

 * @params:	Pointer to ti_sci_msg_rm_udmap_flow_cfg RX FLOW config

 *		structure

 *

 * Return: 0 if all went well, else returns appropriate error value.

 *

 * See @ti_sci_msg_rm_udmap_flow_cfg and @ti_sci_msg_rm_udmap_flow_cfg_req for

 * more info.

 */

static int ti_sci_cmd_rm_udmap_rx_flow_cfg(const struct ti_sci_handle *handle,

			const struct ti_sci_msg_rm_udmap_flow_cfg *params)

{

	struct ti_sci_msg_rm_udmap_flow_cfg_req *req;

	struct ti_sci_msg_hdr *resp;

	struct ti_sci_xfer *xfer;

	struct ti_sci_info *info;

	struct device *dev;

	int ret = 0;



	if (IS_ERR_OR_NULL(handle))

		return -EINVAL;



	info = handle_to_ti_sci_info(handle);

	dev = info->dev;



	xfer = ti_sci_get_one_xfer(info, TISCI_MSG_RM_UDMAP_FLOW_CFG,

				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,

				   sizeof(*req), sizeof(*resp));

	if (IS_ERR(xfer)) {

		ret = PTR_ERR(xfer);

		dev_err(dev, "RX_FL_CFG: Message alloc failed(%d)\n", ret);

		return ret;

	}

	req = (struct ti_sci_msg_rm_udmap_flow_cfg_req *)xfer->xfer_buf;

	req->valid_params = params->valid_params;

	req->nav_id = params->nav_id;

	req->flow_index = params->flow_index;

	req->rx_einfo_present = params->rx_einfo_present;

	req->rx_psinfo_present = params->rx_psinfo_present;

	req->rx_error_handling = params->rx_error_handling;

	req->rx_desc_type = params->rx_desc_type;

	req->rx_sop_offset = params->rx_sop_offset;

	req->rx_dest_qnum = params->rx_dest_qnum;

	req->rx_src_tag_hi = params->rx_src_tag_hi;

	req->rx_src_tag_lo = params->rx_src_tag_lo;

	req->rx_dest_tag_hi = params->rx_dest_tag_hi;

	req->rx_dest_tag_lo = params->rx_dest_tag_lo;

	req->rx_src_tag_hi_sel = params->rx_src_tag_hi_sel;

	req->rx_src_tag_lo_sel = params->rx_src_tag_lo_sel;

	req->rx_dest_tag_hi_sel = params->rx_dest_tag_hi_sel;

	req->rx_dest_tag_lo_sel = params->rx_dest_tag_lo_sel;

	req->rx_fdq0_sz0_qnum = params->rx_fdq0_sz0_qnum;

	req->rx_fdq1_qnum = params->rx_fdq1_qnum;

	req->rx_fdq2_qnum = params->rx_fdq2_qnum;

	req->rx_fdq3_qnum = params->rx_fdq3_qnum;

	req->rx_ps_location = params->rx_ps_location;



	ret = ti_sci_do_xfer(info, xfer);

	if (ret) {

		dev_err(dev, "RX_FL_CFG: Mbox send fail %d\n", ret);

		goto fail;

	}



	resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;

	ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;



fail:

	ti_sci_put_one_xfer(&info->minfo, xfer);

	dev_dbg(info->dev, "RX_FL_CFG: %u ret:%d\n", params->flow_index, ret);

	return ret;

}



/*

 * ti_sci_setup_ops() - Setup the operations structures

 * @info:	pointer to TISCI pointer
@@ -2016,6 +2491,9 @@ static void ti_sci_setup_ops(struct ti_sci_info *info) 
	struct ti_sci_clk_ops *cops = &ops->clk_ops;

	struct ti_sci_rm_core_ops *rm_core_ops = &ops->rm_core_ops;

	struct ti_sci_rm_irq_ops *iops = &ops->rm_irq_ops;

	struct ti_sci_rm_ringacc_ops *rops = &ops->rm_ring_ops;

	struct ti_sci_rm_psil_ops *psilops = &ops->rm_psil_ops;

	struct ti_sci_rm_udmap_ops *udmap_ops = &ops->rm_udmap_ops;



	core_ops->reboot_device = ti_sci_cmd_core_reboot;
@@ -2055,6 +2533,16 @@ static void ti_sci_setup_ops(struct ti_sci_info *info) 
	iops->set_event_map = ti_sci_cmd_set_event_map;

	iops->free_irq = ti_sci_cmd_free_irq;

	iops->free_event_map = ti_sci_cmd_free_event_map;



	rops->config = ti_sci_cmd_ring_config;

	rops->get_config = ti_sci_cmd_ring_get_config;



	psilops->pair = ti_sci_cmd_rm_psil_pair;

	psilops->unpair = ti_sci_cmd_rm_psil_unpair;



	udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg;

	udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg;

	udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg;

}



/**

drivers/firmware/ti_sci.h

+675 −0

File changed.

Preview size limit exceeded, changes collapsed.

include/linux/soc/ti/ti_sci_protocol.h

+215 −0
Original line number Diff line number Diff line
@@ -241,6 +241,218 @@ struct ti_sci_rm_irq_ops { 
			      u16 global_event, u8 vint_status_bit);

};



/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */

#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID	BIT(0)

/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */

#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID	BIT(1)

 /* RA config.count parameter is valid for RM ring configure TI_SCI message */

#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID	BIT(2)

/* RA config.mode parameter is valid for RM ring configure TI_SCI message */

#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID	BIT(3)

/* RA config.size parameter is valid for RM ring configure TI_SCI message */

#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID	BIT(4)

/* RA config.order_id parameter is valid for RM ring configure TISCI message */

#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID	BIT(5)



#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \

	(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \

	TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \

	TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \

	TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \

	TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)



/**

 * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations

 * @config: configure the SoC Navigator Subsystem Ring Accelerator ring

 * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring

 *		configuration

 */

struct ti_sci_rm_ringacc_ops {

	int (*config)(const struct ti_sci_handle *handle,

		      u32 valid_params, u16 nav_id, u16 index,

		      u32 addr_lo, u32 addr_hi, u32 count, u8 mode,

		      u8 size, u8 order_id

	);

	int (*get_config)(const struct ti_sci_handle *handle,

			  u32 nav_id, u32 index, u8 *mode,

			  u32 *addr_lo, u32 *addr_hi, u32 *count,

			  u8 *size, u8 *order_id);

};



/**

 * struct ti_sci_rm_psil_ops - PSI-L thread operations

 * @pair: pair PSI-L source thread to a destination thread.

 *	If the src_thread is mapped to UDMA tchan, the corresponding channel's

 *	TCHAN_THRD_ID register is updated.

 *	If the dst_thread is mapped to UDMA rchan, the corresponding channel's

 *	RCHAN_THRD_ID register is updated.

 * @unpair: unpair PSI-L source thread from a destination thread.

 *	If the src_thread is mapped to UDMA tchan, the corresponding channel's

 *	TCHAN_THRD_ID register is cleared.

 *	If the dst_thread is mapped to UDMA rchan, the corresponding channel's

 *	RCHAN_THRD_ID register is cleared.

 */

struct ti_sci_rm_psil_ops {

	int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,

		    u32 src_thread, u32 dst_thread);

	int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,

		      u32 src_thread, u32 dst_thread);

};



/* UDMAP channel types */

#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR		2

#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB		3	/* RX only */

#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR		10

#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR		11

#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR	12

#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR	13



#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST		0

#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO		2



#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES	1

#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES	2

#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES	3



/* UDMAP TX/RX channel valid_params common declarations */

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID		BIT(0)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID                BIT(1)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID            BIT(2)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID           BIT(3)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID              BIT(4)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID             BIT(5)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID                  BIT(6)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID             BIT(7)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID       BIT(8)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID		BIT(14)



/**

 * Configures a Navigator Subsystem UDMAP transmit channel

 *

 * Configures a Navigator Subsystem UDMAP transmit channel registers.

 * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req

 */

struct ti_sci_msg_rm_udmap_tx_ch_cfg {

	u32 valid_params;

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID        BIT(9)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID      BIT(10)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID        BIT(11)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID      BIT(12)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID            BIT(13)

	u16 nav_id;

	u16 index;

	u8 tx_pause_on_err;

	u8 tx_filt_einfo;

	u8 tx_filt_pswords;

	u8 tx_atype;

	u8 tx_chan_type;

	u8 tx_supr_tdpkt;

	u16 tx_fetch_size;

	u8 tx_credit_count;

	u16 txcq_qnum;

	u8 tx_priority;

	u8 tx_qos;

	u8 tx_orderid;

	u16 fdepth;

	u8 tx_sched_priority;

	u8 tx_burst_size;

};



/**

 * Configures a Navigator Subsystem UDMAP receive channel

 *

 * Configures a Navigator Subsystem UDMAP receive channel registers.

 * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req

 */

struct ti_sci_msg_rm_udmap_rx_ch_cfg {

	u32 valid_params;

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID      BIT(9)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID        BIT(10)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID      BIT(11)

#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID       BIT(12)

	u16 nav_id;

	u16 index;

	u16 rx_fetch_size;

	u16 rxcq_qnum;

	u8 rx_priority;

	u8 rx_qos;

	u8 rx_orderid;

	u8 rx_sched_priority;

	u16 flowid_start;

	u16 flowid_cnt;

	u8 rx_pause_on_err;

	u8 rx_atype;

	u8 rx_chan_type;

	u8 rx_ignore_short;

	u8 rx_ignore_long;

	u8 rx_burst_size;

};



/**

 * Configures a Navigator Subsystem UDMAP receive flow

 *

 * Configures a Navigator Subsystem UDMAP receive flow's registers.

 * See @tis_ci_msg_rm_udmap_flow_cfg_req

 */

struct ti_sci_msg_rm_udmap_flow_cfg {

	u32 valid_params;

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID	BIT(0)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID     BIT(1)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID     BIT(2)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID          BIT(3)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID         BIT(4)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID          BIT(5)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID         BIT(6)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID         BIT(7)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID        BIT(8)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID        BIT(9)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID     BIT(10)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID     BIT(11)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID    BIT(12)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID    BIT(13)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID      BIT(14)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID          BIT(15)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID          BIT(16)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID          BIT(17)

#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID        BIT(18)

	u16 nav_id;

	u16 flow_index;

	u8 rx_einfo_present;

	u8 rx_psinfo_present;

	u8 rx_error_handling;

	u8 rx_desc_type;

	u16 rx_sop_offset;

	u16 rx_dest_qnum;

	u8 rx_src_tag_hi;

	u8 rx_src_tag_lo;

	u8 rx_dest_tag_hi;

	u8 rx_dest_tag_lo;

	u8 rx_src_tag_hi_sel;

	u8 rx_src_tag_lo_sel;

	u8 rx_dest_tag_hi_sel;

	u8 rx_dest_tag_lo_sel;

	u16 rx_fdq0_sz0_qnum;

	u16 rx_fdq1_qnum;

	u16 rx_fdq2_qnum;

	u16 rx_fdq3_qnum;

	u8 rx_ps_location;

};



/**

 * struct ti_sci_rm_udmap_ops - UDMA Management operations

 * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.

 * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.

 * @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.

 */

struct ti_sci_rm_udmap_ops {

	int (*tx_ch_cfg)(const struct ti_sci_handle *handle,

			 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);

	int (*rx_ch_cfg)(const struct ti_sci_handle *handle,

			 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);

	int (*rx_flow_cfg)(const struct ti_sci_handle *handle,

			   const struct ti_sci_msg_rm_udmap_flow_cfg *params);

};



/**

 * struct ti_sci_ops - Function support for TI SCI

 * @dev_ops:	Device specific operations
@@ -254,6 +466,9 @@ struct ti_sci_ops { 
	struct ti_sci_clk_ops clk_ops;

	struct ti_sci_rm_core_ops rm_core_ops;

	struct ti_sci_rm_irq_ops rm_irq_ops;

	struct ti_sci_rm_ringacc_ops rm_ring_ops;

	struct ti_sci_rm_psil_ops rm_psil_ops;

	struct ti_sci_rm_udmap_ops rm_udmap_ops;

};



/**

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