powerpc/8xx: Always pin TLBs at startup. (684c1664) · Commits · 戴 / test

arch/powerpc/kernel/head_8xx.S

+17 −14

Original line number	Diff line number	Diff line
		@@ -765,6 +765,14 @@ start_here:
		mtspr SPRN_MD_RPN, r0
		lis r0, (MD_TWAM \| MD_RSV4I)@h
		mtspr SPRN_MD_CTR, r0
		#endif
		#ifndef CONFIG_PIN_TLB_TEXT
		li r0, 0
		mtspr SPRN_MI_CTR, r0
		#endif
		#if !defined(CONFIG_PIN_TLB_DATA) && !defined(CONFIG_PIN_TLB_IMMR)
		lis r0, MD_TWAM@h
		mtspr SPRN_MD_CTR, r0
		#endif
		tlbia /* Clear all TLB entries */
		sync /* wait for tlbia/tlbie to finish */
		@@ -802,10 +810,6 @@ initial_mmu:
		mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */

		tlbia /* Invalidate all TLB entries */
		#ifdef CONFIG_PIN_TLB_DATA
		oris r10, r10, MD_RSV4I@h
		mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
		#endif

		lis r8, MI_APG_INIT@h /* Set protection modes */
		ori r8, r8, MI_APG_INIT@l
		@@ -814,33 +818,32 @@ initial_mmu:
		ori r8, r8, MD_APG_INIT@l
		mtspr SPRN_MD_AP, r8

		/* Now map the lower RAM (up to 32 Mbytes) into the ITLB. */
		#ifdef CONFIG_PIN_TLB_TEXT
		/* Map the lower RAM (up to 32 Mbytes) into the ITLB and DTLB */
		lis r8, MI_RSV4I@h
		ori r8, r8, 0x1c00
		#endif
		oris r12, r10, MD_RSV4I@h
		ori r12, r12, 0x1c00
		li r9, 4 /* up to 4 pages of 8M */
		mtctr r9
		lis r9, KERNELBASE@h /* Create vaddr for TLB */
		li r10, MI_PS8MEG \| MI_SVALID /* Set 8M byte page */
		li r11, MI_BOOTINIT /* Create RPN for address 0 */
		lis r12, _einittext@h
		ori r12, r12, _einittext@l
		1:
		#ifdef CONFIG_PIN_TLB_TEXT
		mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
		addi r8, r8, 0x100
		#endif

		ori r0, r9, MI_EVALID /* Mark it valid */
		mtspr SPRN_MI_EPN, r0
		mtspr SPRN_MI_TWC, r10
		mtspr SPRN_MI_RPN, r11 /* Store TLB entry */
		mtspr SPRN_MD_CTR, r12
		addi r12, r12, 0x100
		mtspr SPRN_MD_EPN, r0
		mtspr SPRN_MD_TWC, r10
		mtspr SPRN_MD_RPN, r11
		addis r9, r9, 0x80
		addis r11, r11, 0x80

		cmpl cr0, r9, r12
		bdnzf gt, 1b
		bdnz 1b

		/* Since the cache is enabled according to the information we
		* just loaded into the TLB, invalidate and enable the caches here.

arch/powerpc/mm/nohash/8xx.c

+1 −18

Original line number	Diff line number	Diff line
		@@ -62,23 +62,6 @@ unsigned long p_block_mapped(phys_addr_t pa)
		*/
		void __init MMU_init_hw(void)
		{
		/* PIN up to the 3 first 8Mb after IMMR in DTLB table */
		if (IS_ENABLED(CONFIG_PIN_TLB_DATA)) {
		unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000;
		unsigned long flags = 0xf0 \| MD_SPS16K \| _PAGE_SH \| _PAGE_DIRTY;
		int i = 28;
		unsigned long addr = 0;
		unsigned long mem = total_lowmem;

		for (; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) {
		mtspr(SPRN_MD_CTR, ctr \| (i << 8));
		mtspr(SPRN_MD_EPN, (unsigned long)__va(addr) \| MD_EVALID);
		mtspr(SPRN_MD_TWC, MD_PS8MEG \| MD_SVALID);
		mtspr(SPRN_MD_RPN, addr \| flags \| _PAGE_PRESENT);
		addr += LARGE_PAGE_SIZE_8M;
		mem -= LARGE_PAGE_SIZE_8M;
		}
		}
		}

		static bool immr_is_mapped __initdata;
		@@ -223,7 +206,7 @@ void __init setup_initial_memory_limit(phys_addr_t first_memblock_base,
		BUG_ON(first_memblock_base != 0);

		/* 8xx can only access 32MB at the moment */
		memblock_set_current_limit(min_t(u64, first_memblock_size, 0x02000000));
		memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_32M));
		}

		/*

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