Commit 683d672c authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/ehl/dsi: Enable AFE over PPI strap 



The other additional step in the DSI sequence for EHL.

v2:
- Using REG_BIT()(Matt)
- Fixed commit message typo(Vandita)

BSpec: 20597
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619233134.20009-2-jose.souza@intel.com
parent 6a7bafe8

drivers/gpu/drm/i915/display/icl_dsi.c

+8 −0
Original line number Diff line number Diff line
@@ -544,6 +544,14 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) 
			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);

		}

	}



	if (IS_ELKHARTLAKE(dev_priv)) {

		for_each_dsi_port(port, intel_dsi->ports) {

			tmp = I915_READ(ICL_DPHY_CHKN(port));

			tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;

			I915_WRITE(ICL_DPHY_CHKN(port), tmp);

		}

	}

}



static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -1993,6 +1993,10 @@ enum i915_power_well_id { 
#define   N_SCALAR(x)			((x) << 24)

#define   N_SCALAR_MASK			(0x7F << 24)



#define _ICL_DPHY_CHKN_REG			0x194

#define ICL_DPHY_CHKN(port)			_MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)

#define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)



#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \

	_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))

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