Commit 682d055e authored by Valentin Raevsky's avatar Valentin Raevsky Committed by Shawn Guo
Browse files

ARM: dts: Add initial support for cm-fx6. 



Add initial support for cm-fx6 module.

cm-fx6 is a module based on mx6q SoC with the following features:
- Up to 4GB of DDR3
- 1 LCD/DVI output port
- 1 HDMI output port
- 2 LVDS LCD ports
- Gigabit Ethernet
- Analog Audio
- CAN
- SATA
- NAND
- PCIE

This patch allows to boot up the module, configures the serial console,
the Ethernet adapter and the heartbeat led.

cm-fx6 is embedded inside the Utilite computer.

Signed-off-by: default avatarValentin Raevsky <valentin@compulab.co.il>
Signed-off-by: default avatarIgor Grinberg <grinberg@compulab.co.il>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 67339b35

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -162,6 +162,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ 
	imx6dl-sabresd.dtb \

	imx6dl-wandboard.dtb \

	imx6q-arm2.dtb \

	imx6q-cm-fx6.dtb \

	imx6q-cubox-i.dtb \

	imx6q-gw51xx.dtb \

	imx6q-gw52xx.dtb \

arch/arm/boot/dts/imx6q-cm-fx6.dts

0 → 100644
+107 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 CompuLab Ltd.

 *

 * Author: Valentin Raevsky <valentin@compulab.co.il>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/dts-v1/;

#include "imx6q.dtsi"



/ {

	model = "CompuLab CM-FX6";

	compatible = "compulab,cm-fx6", "fsl,imx6q";



	memory {

		reg = <0x10000000 0x80000000>;

	};



	leds {

		compatible = "gpio-leds";



		heartbeat-led {

			label = "Heartbeat";

			gpios = <&gpio2 31 0>;

			linux,default-trigger = "heartbeat";

		};

	};

};



&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet>;

	phy-mode = "rgmii";

	status = "okay";

};



&gpmi {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gpmi_nand>;

	status = "okay";

};



&iomuxc {

	imx6q-cm-fx6 {

		pinctrl_enet: enetgrp {

			fsl,pins = <

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8

			>;

		};



		pinctrl_gpmi_nand: gpminandgrp {

			fsl,pins = <

				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1

				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1

				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1

				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000

				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1

				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1

				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1

				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1

				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1

				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1

				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1

				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1

				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1

				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1

				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1

				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1

				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1

			>;

		};



		pinctrl_uart4: uart4grp {

			fsl,pins = <

				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1

				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1

			>;

		};

	};

};



&uart4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart4>;

	status = "okay";

};

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