Commit 6822a84d authored by Will Deacon's avatar Will Deacon Committed by Ingo Molnar
Browse files

locking/atomic, arch/arm64: Generate LSE non-return cases using common macros 



atomic[64]_{add,and,andnot,or,xor} all follow the same patterns, so
generate them using macros, like we do for the LL/SC case already.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Steve Capper <steve.capper@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arch@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/1461344493-8262-1-git-send-email-will.deacon@arm.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent e490f9b1

arch/arm64/include/asm/atomic_lse.h

+32 −90
Original line number Diff line number Diff line
@@ -26,54 +26,25 @@ 
#endif



#define __LL_SC_ATOMIC(op)	__LL_SC_CALL(atomic_##op)



static inline void atomic_andnot(int i, atomic_t *v)

{

	register int w0 asm ("w0") = i;

	register atomic_t *x1 asm ("x1") = v;



	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(andnot),

	"	stclr	%w[i], %[v]\n")

	: [i] "+r" (w0), [v] "+Q" (v->counter)

	: "r" (x1)

	: __LL_SC_CLOBBERS);

}



static inline void atomic_or(int i, atomic_t *v)

{

	register int w0 asm ("w0") = i;

	register atomic_t *x1 asm ("x1") = v;



	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(or),

	"	stset	%w[i], %[v]\n")

	: [i] "+r" (w0), [v] "+Q" (v->counter)

	: "r" (x1)

	: __LL_SC_CLOBBERS);

}



static inline void atomic_xor(int i, atomic_t *v)

{

	register int w0 asm ("w0") = i;

	register atomic_t *x1 asm ("x1") = v;



	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(xor),

	"	steor	%w[i], %[v]\n")

	: [i] "+r" (w0), [v] "+Q" (v->counter)

	: "r" (x1)

	: __LL_SC_CLOBBERS);

#define ATOMIC_OP(op, asm_op)						\

static inline void atomic_##op(int i, atomic_t *v)			\

{									\

	register int w0 asm ("w0") = i;					\

	register atomic_t *x1 asm ("x1") = v;				\

									\

	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(op),		\

"	" #asm_op "	%w[i], %[v]\n")					\

	: [i] "+r" (w0), [v] "+Q" (v->counter)				\

	: "r" (x1)							\

	: __LL_SC_CLOBBERS);						\

}



static inline void atomic_add(int i, atomic_t *v)

{

	register int w0 asm ("w0") = i;

	register atomic_t *x1 asm ("x1") = v;

ATOMIC_OP(andnot, stclr)

ATOMIC_OP(or, stset)

ATOMIC_OP(xor, steor)

ATOMIC_OP(add, stadd)



	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(add),

	"	stadd	%w[i], %[v]\n")

	: [i] "+r" (w0), [v] "+Q" (v->counter)

	: "r" (x1)

	: __LL_SC_CLOBBERS);

}

#undef ATOMIC_OP



#define ATOMIC_OP_ADD_RETURN(name, mb, cl...)				\

static inline int atomic_add_return##name(int i, atomic_t *v)		\
@@ -167,54 +138,25 @@ ATOMIC_OP_SUB_RETURN( , al, "memory") 
#undef __LL_SC_ATOMIC



#define __LL_SC_ATOMIC64(op)	__LL_SC_CALL(atomic64_##op)



static inline void atomic64_andnot(long i, atomic64_t *v)

{

	register long x0 asm ("x0") = i;

	register atomic64_t *x1 asm ("x1") = v;



	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(andnot),

	"	stclr	%[i], %[v]\n")

	: [i] "+r" (x0), [v] "+Q" (v->counter)

	: "r" (x1)

	: __LL_SC_CLOBBERS);

}



static inline void atomic64_or(long i, atomic64_t *v)

{

	register long x0 asm ("x0") = i;

	register atomic64_t *x1 asm ("x1") = v;



	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(or),

	"	stset	%[i], %[v]\n")

	: [i] "+r" (x0), [v] "+Q" (v->counter)

	: "r" (x1)

	: __LL_SC_CLOBBERS);

}



static inline void atomic64_xor(long i, atomic64_t *v)

{

	register long x0 asm ("x0") = i;

	register atomic64_t *x1 asm ("x1") = v;



	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(xor),

	"	steor	%[i], %[v]\n")

	: [i] "+r" (x0), [v] "+Q" (v->counter)

	: "r" (x1)

	: __LL_SC_CLOBBERS);

#define ATOMIC64_OP(op, asm_op)						\

static inline void atomic64_##op(long i, atomic64_t *v)			\

{									\

	register long x0 asm ("x0") = i;				\

	register atomic64_t *x1 asm ("x1") = v;				\

									\

	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(op),	\

"	" #asm_op "	%[i], %[v]\n")					\

	: [i] "+r" (x0), [v] "+Q" (v->counter)				\

	: "r" (x1)							\

	: __LL_SC_CLOBBERS);						\

}



static inline void atomic64_add(long i, atomic64_t *v)

{

	register long x0 asm ("x0") = i;

	register atomic64_t *x1 asm ("x1") = v;

ATOMIC64_OP(andnot, stclr)

ATOMIC64_OP(or, stset)

ATOMIC64_OP(xor, steor)

ATOMIC64_OP(add, stadd)



	asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(add),

	"	stadd	%[i], %[v]\n")

	: [i] "+r" (x0), [v] "+Q" (v->counter)

	: "r" (x1)

	: __LL_SC_CLOBBERS);

}

#undef ATOMIC64_OP



#define ATOMIC64_OP_ADD_RETURN(name, mb, cl...)				\

static inline long atomic64_add_return##name(long i, atomic64_t *v)	\

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