clk: tegra: Fix PLLD mnp table (67fc26bf) · Commits · 戴 / test

PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by:

drivers/clk/tegra/clk-tegra124.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -570,6 +570,15 @@ static struct tegra_clk_pll_params pll_a_params = {
		.flags = TEGRA_PLL_HAS_CPCON \| TEGRA_PLL_USE_LOCK,
		};

		static struct div_nmp plld_nmp = {
		.divm_shift = 0,
		.divm_width = 5,
		.divn_shift = 8,
		.divn_width = 11,
		.divp_shift = 20,
		.divp_width = 3,
		};

		static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
		{12000000, 216000000, 864, 12, 4, 12},
		{13000000, 216000000, 864, 13, 4, 12},
		@@ -603,7 +612,7 @@ static struct tegra_clk_pll_params pll_d_params = {
		.lock_mask = PLL_BASE_LOCK,
		.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
		.lock_delay = 1000,
		.div_nmp = &pllp_nmp,
		.div_nmp = &plld_nmp,
		.freq_table = pll_d_freq_table,
		.flags = TEGRA_PLL_HAS_CPCON \| TEGRA_PLL_SET_LFCON \|
		TEGRA_PLL_USE_LOCK,