Commit 67e45621 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:
 "A handful of build fixes, all found by Huawei's autobuilder.

  None of these patches should have any functional impact on kernels
  that build, and they're mostly related to various features
  intermingling with !MMU.

  While some of these might be better hoisted to generic code, it seems
  better to have the simple fixes in the meanwhile.

  As far as I know these are the only outstanding patches for 5.7"

* tag 'riscv-for-linus-5.7-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: mmiowb: Fix implicit declaration of function 'smp_processor_id'
  riscv: pgtable: Fix __kernel_map_pages build error if NOMMU
  riscv: Make SYS_SUPPORTS_HUGETLBFS depends on MMU
  riscv: Disable ARCH_HAS_DEBUG_VIRTUAL if NOMMU
  riscv: Add pgprot_writecombine/device and PAGE_SHARED defination if NOMMU
  riscv: stacktrace: Fix undefined reference to `walk_stackframe'
  riscv: Fix unmet direct dependencies built based on SOC_VIRT
  riscv: perf: RISCV_BASE_PMU should be independent
  riscv: perf_event: Make some funciton static
parents 01d8a748 ed1ed4c0

arch/riscv/Kconfig

+2 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ config RISCV 
	select GENERIC_ARCH_TOPOLOGY if SMP

	select ARCH_HAS_PTE_SPECIAL

	select ARCH_HAS_MMIOWB

	select ARCH_HAS_DEBUG_VIRTUAL

	select ARCH_HAS_DEBUG_VIRTUAL if MMU

	select HAVE_EBPF_JIT if MMU

	select EDAC_SUPPORT

	select ARCH_HAS_GIGANTIC_PAGE
@@ -136,6 +136,7 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC 
	def_bool y



config SYS_SUPPORTS_HUGETLBFS

	depends on MMU

	def_bool y



config STACKTRACE_SUPPORT

arch/riscv/Kconfig.socs

+9 −8
Original line number Diff line number Diff line
@@ -12,10 +12,11 @@ config SOC_SIFIVE 


config SOC_VIRT

	bool "QEMU Virt Machine"

	select POWER_RESET

	select POWER_RESET_SYSCON

	select POWER_RESET_SYSCON_POWEROFF

	select GOLDFISH

       select RTC_DRV_GOLDFISH

	select RTC_DRV_GOLDFISH if RTC_CLASS

	select SIFIVE_PLIC

	help

	  This enables support for QEMU Virt Machine.

arch/riscv/include/asm/mmio.h

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 


#ifndef CONFIG_MMU

#define pgprot_noncached(x)	(x)

#define pgprot_writecombine(x)	(x)

#define pgprot_device(x)	(x)

#endif /* CONFIG_MMU */



/* Generic IO read/write.  These perform native-endian accesses. */

arch/riscv/include/asm/mmiowb.h

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 */

#define mmiowb()	__asm__ __volatile__ ("fence o,w" : : : "memory");



#include <linux/smp.h>

#include <asm-generic/mmiowb.h>



#endif	/* _ASM_RISCV_MMIOWB_H */

arch/riscv/include/asm/perf_event.h

+2 −6
Original line number Diff line number Diff line
@@ -12,19 +12,14 @@ 
#include <linux/ptrace.h>

#include <linux/interrupt.h>



#ifdef CONFIG_RISCV_BASE_PMU

#define RISCV_BASE_COUNTERS	2



/*

 * The RISCV_MAX_COUNTERS parameter should be specified.

 */



#ifdef CONFIG_RISCV_BASE_PMU

#define RISCV_MAX_COUNTERS	2

#endif



#ifndef RISCV_MAX_COUNTERS

#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU."

#endif



/*

 * These are the indexes of bits in counteren register *minus* 1,
@@ -82,6 +77,7 @@ struct riscv_pmu { 
	int		irq;

};



#endif

#ifdef CONFIG_PERF_EVENTS

#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs

#endif

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