arm64: Lower priority mask for GIC_PRIO_IRQON (677379bc) · Commits · 戴 / test

On a system with two security states, if SCR_EL3.FIQ is cleared, non-secure IRQ priorities get shifted to fit the secure view but priority masks aren't. On such system, it turns out that GIC_PRIO_IRQON masks the priority of normal interrupts, which obviously ends up in a hang. Increase GIC_PRIO_IRQON value (i.e. lower priority) to make sure interrupts are not blocked by it. Cc: Oleg Nesterov <oleg@redhat.com> Fixes: ("arm64: Fix incorrect irqflag restore for priority masking") Acked-by:

Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:

Julien Thierry <julien.thierry.kdev@gmail.com> Signed-off-by:

Catalin Marinas <catalin.marinas@arm.com> [will: fixed Fixes: tag] Signed-off-by:

Will Deacon <will@kernel.org>

arch/arm64/include/asm/arch_gicv3.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -155,6 +155,12 @@ static inline void gic_pmr_mask_irqs(void)
		BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF \|
		GIC_PRIO_PSR_I_SET));
		BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
		/*
		* Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
		* and non-secure PMR accesses are not subject to the shifts that
		* are applied to IRQ priorities
		*/
		BUILD_BUG_ON((0x80 \| (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
		gic_write_pmr(GIC_PRIO_IRQOFF);
		}

arch/arm64/include/asm/ptrace.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -30,7 +30,7 @@
		* in the the priority mask, it indicates that PSR.I should be set and
		* interrupt disabling temporarily does not rely on IRQ priorities.
		*/
		#define GIC_PRIO_IRQON 0xc0
		#define GIC_PRIO_IRQON 0xe0
		#define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80)
		#define GIC_PRIO_PSR_I_SET (1 << 4)

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