Commit 675d12ac authored Sep 17, 2020 by Nicolin Chen Committed by Joerg Roedel Sep 18, 2020

memory: tegra: Correct num_tlb_lines for tegra210



According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES
field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines
should be 48 (0x30) rather than 32 (0x20).

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20200917113155.13438-3-nicoleotsuka@gmail.com


Signed-off-by: Joerg Roedel <jroedel@suse.de>

parent d5c152c3

drivers/memory/tegra/tegra210.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1073,7 +1073,7 @@ static const struct tegra_smmu_soc tegra210_smmu_soc = {
		.num_groups = ARRAY_SIZE(tegra210_groups),
		.supports_round_robin_arbitration = true,
		.supports_request_limit = true,
		.num_tlb_lines = 32,
		.num_tlb_lines = 48,
		.num_asids = 128,
		};

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