Commit 6747c202 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn:Update DPG mode VCN memory control 



Update Dynamic Power Gate mode VCN memory control

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cce9d555

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+11 −8
Original line number Diff line number Diff line
@@ -983,11 +983,13 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 


	/* initialize VCN memory controller */

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,

		(0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |

		(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |

		UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |

		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |

		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |

		UVD_LMI_CTRL__REQ_MODE_MASK |

		UVD_LMI_CTRL__CRC_RESET_MASK |

		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |

		0x00100000L, 0xFFFFFFFF, 0);



#ifdef __BIG_ENDIAN
@@ -1041,13 +1043,14 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 
	vcn_v1_0_clock_gating_dpg_mode(adev, 1);

	/* setup mmUVD_LMI_CTRL */

	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,

			(UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |

				UVD_LMI_CTRL__CRC_RESET_MASK |

				UVD_LMI_CTRL__MASK_MC_URGENT_MASK |

		(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |

		UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |

		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |

		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |

				(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |

				0x00100000L), 0xFFFFFFFF, 1);

		UVD_LMI_CTRL__REQ_MODE_MASK |

		UVD_LMI_CTRL__CRC_RESET_MASK |

		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |

		0x00100000L, 0xFFFFFFFF, 1);



	tmp = adev->gfx.config.gb_addr_config;

	/* setup VCN global tiling registers */

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