Commit 6741c4bb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_fixes_4.17_2' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips 

Pull MIPS fixes from James Hogan:

 - fix build with DEBUG_ZBOOT and MACH_JZ4770 (4.16)

 - include xilfpga FDT in fitImage and stop generating dtb.o (4.15)

 - fix software IO coherence on CM SMP systems (4.8)

 - ptrace: Fix PEEKUSR/POKEUSR to o32 FGRs (3.14)

 - ptrace: Expose FIR register through FP regset (3.13)

 - fix typo in KVM debugfs file name (3.10)

* tag 'mips_fixes_4.17_2' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips:
  MIPS: Fix ptrace(2) PTRACE_PEEKUSR and PTRACE_POKEUSR accesses to o32 FGRs
  MIPS: xilfpga: Actually include FDT in fitImage
  MIPS: xilfpga: Stop generating useless dtb.o
  KVM: Fix spelling mistake: "cop_unsuable" -> "cop_unusable"
  MIPS: ptrace: Expose FIR register through FP regset
  MIPS: Fix build with DEBUG_ZBOOT and MACH_JZ4770
  MIPS: c-r4k: Fix data corruption related to cache coherence
parents 5aef268a 9a3a92cc

arch/mips/boot/compressed/uart-16550.c

+3 −3
Original line number Diff line number Diff line
@@ -18,9 +18,9 @@ 
#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))

#endif



#if defined(CONFIG_MACH_JZ4740) || defined(CONFIG_MACH_JZ4780)

#include <asm/mach-jz4740/base.h>

#define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset))

#ifdef CONFIG_MACH_INGENIC

#define INGENIC_UART0_BASE_ADDR	0x10030000

#define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset))

#endif



#ifdef CONFIG_CPU_XLR

arch/mips/boot/dts/xilfpga/Makefile

+0 −2
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA)	+= nexys4ddr.dtb
 


obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))

arch/mips/generic/Platform

+1 −0
Original line number Diff line number Diff line
@@ -16,3 +16,4 @@ all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb 
its-y					:= vmlinux.its.S

its-$(CONFIG_FIT_IMAGE_FDT_BOSTON)	+= board-boston.its.S

its-$(CONFIG_FIT_IMAGE_FDT_NI169445)	+= board-ni169445.its.S

its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA)	+= board-xilfpga.its.S

arch/mips/kernel/ptrace.c

+18 −4
Original line number Diff line number Diff line
@@ -463,7 +463,7 @@ static int fpr_get_msa(struct task_struct *target, 
/*

 * Copy the floating-point context to the supplied NT_PRFPREG buffer.

 * Choose the appropriate helper for general registers, and then copy

 * the FCSR register separately.

 * the FCSR and FIR registers separately.

 */

static int fpr_get(struct task_struct *target,

		   const struct user_regset *regset,
@@ -471,6 +471,7 @@ static int fpr_get(struct task_struct *target, 
		   void *kbuf, void __user *ubuf)

{

	const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);

	const int fir_pos = fcr31_pos + sizeof(u32);

	int err;



	if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
@@ -483,6 +484,12 @@ static int fpr_get(struct task_struct *target, 
	err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,

				  &target->thread.fpu.fcr31,

				  fcr31_pos, fcr31_pos + sizeof(u32));

	if (err)

		return err;



	err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,

				  &boot_cpu_data.fpu_id,

				  fir_pos, fir_pos + sizeof(u32));



	return err;

}
@@ -531,7 +538,8 @@ static int fpr_set_msa(struct task_struct *target, 
/*

 * Copy the supplied NT_PRFPREG buffer to the floating-point context.

 * Choose the appropriate helper for general registers, and then copy

 * the FCSR register separately.

 * the FCSR register separately.  Ignore the incoming FIR register

 * contents though, as the register is read-only.

 *

 * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',

 * which is supposed to have been guaranteed by the kernel before
@@ -545,6 +553,7 @@ static int fpr_set(struct task_struct *target, 
		   const void *kbuf, const void __user *ubuf)

{

	const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);

	const int fir_pos = fcr31_pos + sizeof(u32);

	u32 fcr31;

	int err;
@@ -572,6 +581,11 @@ static int fpr_set(struct task_struct *target, 
		ptrace_setfcr31(target, fcr31);

	}



	if (count > 0)

		err = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,

						fir_pos,

						fir_pos + sizeof(u32));



	return err;

}
@@ -793,7 +807,7 @@ long arch_ptrace(struct task_struct *child, long request, 
			fregs = get_fpu_regs(child);



#ifdef CONFIG_32BIT

			if (test_thread_flag(TIF_32BIT_FPREGS)) {

			if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {

				/*

				 * The odd registers are actually the high

				 * order bits of the values stored in the even
@@ -888,7 +902,7 @@ long arch_ptrace(struct task_struct *child, long request, 


			init_fp_ctx(child);

#ifdef CONFIG_32BIT

			if (test_thread_flag(TIF_32BIT_FPREGS)) {

			if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {

				/*

				 * The odd registers are actually the high

				 * order bits of the values stored in the even

arch/mips/kernel/ptrace32.c

+2 −2
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 
				break;

			}

			fregs = get_fpu_regs(child);

			if (test_thread_flag(TIF_32BIT_FPREGS)) {

			if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {

				/*

				 * The odd registers are actually the high

				 * order bits of the values stored in the even
@@ -212,7 +212,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, 
				       sizeof(child->thread.fpu));

				child->thread.fpu.fcr31 = 0;

			}

			if (test_thread_flag(TIF_32BIT_FPREGS)) {

			if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {

				/*

				 * The odd registers are actually the high

				 * order bits of the values stored in the even

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