x86/timers/apic: Inform TSC deadline clockevent device about recalibration (6731b0d6) · Commits · 戴 / test

This patch eliminates a source of imprecise APIC timer interrupts, which imprecision may result in double interrupts or even late interrupts. The TSC deadline clockevent devices' configuration and registration happens before the TSC frequency calibration is refined in tsc_refine_calibration_work(). This results in the TSC clocksource and the TSC deadline clockevent devices being configured with slightly different frequencies: the former gets the refined one and the latter are configured with the inaccurate frequency detected earlier by means of the "Fast TSC calibration using PIT". Within the APIC code, introduce the notifier function lapic_update_tsc_freq() which reconfigures all per-CPU TSC deadline clockevent devices with the current tsc_khz. Call it from the TSC code after TSC calibration refinement has happened. Signed-off-by:

Nicolai Stange <nicstange@gmail.com> Signed-off-by:

Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by:

Thomas Gleixner <tglx@linutronix.de> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Borislav Petkov <bp@suse.de> Cc: Christopher S. Hall <christopher.s.hall@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Hidehiro Kawai <hidehiro.kawai.ez@hitachi.com> Cc: Len Brown <len.brown@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> Link: http://lkml.kernel.org/r/20160714152255.18295-3-nicstange@gmail.com [ Pushed #ifdef CONFIG_X86_LOCAL_APIC into header, improved changelog. ] Signed-off-by:

Ingo Molnar <mingo@kernel.org>

arch/x86/include/asm/apic.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -135,6 +135,7 @@ extern void init_apic_mappings(void);
		void register_lapic_address(unsigned long address);
		extern void setup_boot_APIC_clock(void);
		extern void setup_secondary_APIC_clock(void);
		extern void lapic_update_tsc_freq(void);
		extern int APIC_init_uniprocessor(void);

		#ifdef CONFIG_X86_64
		@@ -170,6 +171,7 @@ static inline void init_apic_mappings(void) { }
		static inline void disable_local_APIC(void) { }
		# define setup_boot_APIC_clock x86_init_noop
		# define setup_secondary_APIC_clock x86_init_noop
		static inline void lapic_update_tsc_freq(void) { }
		#endif /* !CONFIG_X86_LOCAL_APIC */

		#ifdef CONFIG_X86_X2APIC

arch/x86/kernel/apic/apic.c

+24 −0

Original line number	Diff line number	Diff line
		@@ -571,6 +571,30 @@ static void setup_APIC_timer(void)
		clockevents_register_device(levt);
		}

		/*
		* Install the updated TSC frequency from recalibration at the TSC
		* deadline clockevent devices.
		*/
		static void __lapic_update_tsc_freq(void *info)
		{
		struct clock_event_device *levt = this_cpu_ptr(&lapic_events);

		if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
		return;

		clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
		}

		void lapic_update_tsc_freq(void)
		{
		/*
		* The clockevent device's ->mult and ->shift can both be
		* changed. In order to avoid races, schedule the frequency
		* update code on each CPU.
		*/
		on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
		}

		/*
		* In this functions we calibrate APIC bus clocks to the external timer.
		*

arch/x86/kernel/tsc.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -22,6 +22,7 @@
		#include <asm/nmi.h>
		#include <asm/x86_init.h>
		#include <asm/geode.h>
		#include <asm/apic.h>

		unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
		EXPORT_SYMBOL(cpu_khz);
		@@ -1249,6 +1250,9 @@ static void tsc_refine_calibration_work(struct work_struct *work)
		(unsigned long)tsc_khz / 1000,
		(unsigned long)tsc_khz % 1000);

		/* Inform the TSC deadline clockevent devices about the recalibration */
		lapic_update_tsc_freq();

		out:
		if (boot_cpu_has(X86_FEATURE_ART))
		art_related_clocksource = &clocksource_tsc;

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