Commit 67171a3f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/avi/kvm:
  x86: disable KVM for Voyager and friends
  KVM: VMX: Avoid rearranging switched guest msrs while they are loaded
  KVM: MMU: Fix race when instantiating a shadow pte
  KVM: Route irq 0 to vcpu 0 exclusively
  KVM: Avoid infinite-frequency local apic timer
  KVM: make MMU_DEBUG compile again
  KVM: move alloc_apic_access_page() outside of non-preemptable region
  KVM: SVM: fix Windows XP 64 bit installation crash
  KVM: remove the usage of the mmap_sem for the protection of the memory slots.
  KVM: emulate access to MSR_IA32_MCG_CTL
  KVM: Make the supported cpuid list a host property rather than a vm property
  KVM: Fix kvm_arch_vcpu_ioctl_set_sregs so that set_cr0 works properly
  KVM: SVM: set NM intercept when enabling CR0.TS in the guest
  KVM: SVM: Fix lazy FPU switching
parents ce932967 1a4e3f89

arch/x86/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ config X86 
	select HAVE_IDE

	select HAVE_OPROFILE

	select HAVE_KPROBES

	select HAVE_KVM

	select HAVE_KVM if ((X86_32 && !X86_VOYAGER && !X86_VISWS && !X86_NUMAQ) || X86_64)





config GENERIC_LOCKBREAK

arch/x86/kvm/lapic.c

+4 −0
Original line number Diff line number Diff line
@@ -647,6 +647,10 @@ static void start_apic_timer(struct kvm_lapic *apic) 
	apic->timer.period = apic_get_reg(apic, APIC_TMICT) *

		    APIC_BUS_CYCLE_NS * apic->timer.divide_count;

	atomic_set(&apic->timer.pending, 0);



	if (!apic->timer.period)

		return;



	hrtimer_start(&apic->timer.dev,

		      ktime_add_ns(now, apic->timer.period),

		      HRTIMER_MODE_ABS);

arch/x86/kvm/mmu.c

+25 −13
Original line number Diff line number Diff line
@@ -681,8 +681,7 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, 
					     unsigned level,

					     int metaphysical,

					     unsigned access,

					     u64 *parent_pte,

					     bool *new_page)

					     u64 *parent_pte)

{

	union kvm_mmu_page_role role;

	unsigned index;
@@ -722,8 +721,6 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, 
	vcpu->arch.mmu.prefetch_page(vcpu, sp);

	if (!metaphysical)

		rmap_write_protect(vcpu->kvm, gfn);

	if (new_page)

		*new_page = 1;

	return sp;

}
@@ -876,11 +873,18 @@ static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn) 


struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)

{

	struct page *page;



	gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);



	if (gpa == UNMAPPED_GVA)

		return NULL;

	return gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);



	down_read(&current->mm->mmap_sem);

	page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);

	up_read(&current->mm->mmap_sem);



	return page;

}



static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
@@ -999,8 +1003,7 @@ static int __nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, 
				>> PAGE_SHIFT;

			new_table = kvm_mmu_get_page(vcpu, pseudo_gfn,

						     v, level - 1,

						     1, ACC_ALL, &table[index],

						     NULL);

						     1, ACC_ALL, &table[index]);

			if (!new_table) {

				pgprintk("nonpaging_map: ENOMEM\n");

				kvm_release_page_clean(page);
@@ -1020,15 +1023,18 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn) 


	struct page *page;



	down_read(&vcpu->kvm->slots_lock);



	down_read(&current->mm->mmap_sem);

	page = gfn_to_page(vcpu->kvm, gfn);

	up_read(&current->mm->mmap_sem);



	spin_lock(&vcpu->kvm->mmu_lock);

	kvm_mmu_free_some_pages(vcpu);

	r = __nonpaging_map(vcpu, v, write, gfn, page);

	spin_unlock(&vcpu->kvm->mmu_lock);



	up_read(&current->mm->mmap_sem);

	up_read(&vcpu->kvm->slots_lock);



	return r;

}
@@ -1090,7 +1096,7 @@ static void mmu_alloc_roots(struct kvm_vcpu *vcpu) 


		ASSERT(!VALID_PAGE(root));

		sp = kvm_mmu_get_page(vcpu, root_gfn, 0,

				      PT64_ROOT_LEVEL, 0, ACC_ALL, NULL, NULL);

				      PT64_ROOT_LEVEL, 0, ACC_ALL, NULL);

		root = __pa(sp->spt);

		++sp->root_count;

		vcpu->arch.mmu.root_hpa = root;
@@ -1111,7 +1117,7 @@ static void mmu_alloc_roots(struct kvm_vcpu *vcpu) 
			root_gfn = 0;

		sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,

				      PT32_ROOT_LEVEL, !is_paging(vcpu),

				      ACC_ALL, NULL, NULL);

				      ACC_ALL, NULL);

		root = __pa(sp->spt);

		++sp->root_count;

		vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
@@ -1172,7 +1178,7 @@ void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu) 


static void paging_new_cr3(struct kvm_vcpu *vcpu)

{

	pgprintk("%s: cr3 %lx\n", __FUNCTION__, vcpu->cr3);

	pgprintk("%s: cr3 %lx\n", __FUNCTION__, vcpu->arch.cr3);

	mmu_free_roots(vcpu);

}
@@ -1362,6 +1368,7 @@ static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, 
	gfn_t gfn;

	int r;

	u64 gpte = 0;

	struct page *page;



	if (bytes != 4 && bytes != 8)

		return;
@@ -1389,6 +1396,11 @@ static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, 
	if (!is_present_pte(gpte))

		return;

	gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;



	down_read(&current->mm->mmap_sem);

	page = gfn_to_page(vcpu->kvm, gfn);

	up_read(&current->mm->mmap_sem);



	vcpu->arch.update_pte.gfn = gfn;

	vcpu->arch.update_pte.page = gfn_to_page(vcpu->kvm, gfn);

}
@@ -1496,9 +1508,9 @@ int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) 
	gpa_t gpa;

	int r;



	down_read(&current->mm->mmap_sem);

	down_read(&vcpu->kvm->slots_lock);

	gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);

	up_read(&current->mm->mmap_sem);

	up_read(&vcpu->kvm->slots_lock);



	spin_lock(&vcpu->kvm->mmu_lock);

	r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);

arch/x86/kvm/paging_tmpl.h

+12 −8
Original line number Diff line number Diff line
@@ -91,7 +91,10 @@ static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, 
	pt_element_t *table;

	struct page *page;



	down_read(&current->mm->mmap_sem);

	page = gfn_to_page(kvm, table_gfn);

	up_read(&current->mm->mmap_sem);



	table = kmap_atomic(page, KM_USER0);



	ret = CMPXCHG(&table[index], orig_pte, new_pte);
@@ -140,7 +143,7 @@ walk: 
	}

#endif

	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||

	       (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	       (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);



	pt_access = ACC_ALL;
@@ -297,7 +300,6 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, 
		u64 shadow_pte;

		int metaphysical;

		gfn_t table_gfn;

		bool new_page = 0;



		shadow_ent = ((u64 *)__va(shadow_addr)) + index;

		if (level == PT_PAGE_TABLE_LEVEL)
@@ -319,8 +321,8 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, 
		}

		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,

					       metaphysical, access,

					       shadow_ent, &new_page);

		if (new_page && !metaphysical) {

					       shadow_ent);

		if (!metaphysical) {

			int r;

			pt_element_t curr_pte;

			r = kvm_read_guest_atomic(vcpu->kvm,
@@ -378,7 +380,7 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, 
	if (r)

		return r;



	down_read(&current->mm->mmap_sem);

	down_read(&vcpu->kvm->slots_lock);

	/*

	 * Look up the shadow pte for the faulting address.

	 */
@@ -392,11 +394,13 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, 
		pgprintk("%s: guest page fault\n", __FUNCTION__);

		inject_page_fault(vcpu, addr, walker.error_code);

		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */

		up_read(&current->mm->mmap_sem);

		up_read(&vcpu->kvm->slots_lock);

		return 0;

	}



	down_read(&current->mm->mmap_sem);

	page = gfn_to_page(vcpu->kvm, walker.gfn);

	up_read(&current->mm->mmap_sem);



	spin_lock(&vcpu->kvm->mmu_lock);

	kvm_mmu_free_some_pages(vcpu);
@@ -413,14 +417,14 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, 
	 */

	if (shadow_pte && is_io_pte(*shadow_pte)) {

		spin_unlock(&vcpu->kvm->mmu_lock);

		up_read(&current->mm->mmap_sem);

		up_read(&vcpu->kvm->slots_lock);

		return 1;

	}



	++vcpu->stat.pf_fixed;

	kvm_mmu_audit(vcpu, "post page fault (fixed)");

	spin_unlock(&vcpu->kvm->mmu_lock);

	up_read(&current->mm->mmap_sem);

	up_read(&vcpu->kvm->slots_lock);



	return write_pt;

}

arch/x86/kvm/svm.c

+26 −0
Original line number Diff line number Diff line
@@ -792,6 +792,10 @@ static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 
	vcpu->arch.cr0 = cr0;

	cr0 |= X86_CR0_PG | X86_CR0_WP;

	cr0 &= ~(X86_CR0_CD | X86_CR0_NW);

	if (!vcpu->fpu_active) {

		svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);

		cr0 |= X86_CR0_TS;

	}

	svm->vmcb->save.cr0 = cr0;

}
@@ -1096,6 +1100,24 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) 
	case MSR_IA32_SYSENTER_ESP:

		*data = svm->vmcb->save.sysenter_esp;

		break;

	/* Nobody will change the following 5 values in the VMCB so

	   we can safely return them on rdmsr. They will always be 0

	   until LBRV is implemented. */

	case MSR_IA32_DEBUGCTLMSR:

		*data = svm->vmcb->save.dbgctl;

		break;

	case MSR_IA32_LASTBRANCHFROMIP:

		*data = svm->vmcb->save.br_from;

		break;

	case MSR_IA32_LASTBRANCHTOIP:

		*data = svm->vmcb->save.br_to;

		break;

	case MSR_IA32_LASTINTFROMIP:

		*data = svm->vmcb->save.last_excp_from;

		break;

	case MSR_IA32_LASTINTTOIP:

		*data = svm->vmcb->save.last_excp_to;

		break;

	default:

		return kvm_get_msr_common(vcpu, ecx, data);

	}
@@ -1156,6 +1178,10 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) 
	case MSR_IA32_SYSENTER_ESP:

		svm->vmcb->save.sysenter_esp = data;

		break;

	case MSR_IA32_DEBUGCTLMSR:

		pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",

				__FUNCTION__, data);

		break;

	case MSR_K7_EVNTSEL0:

	case MSR_K7_EVNTSEL1:

	case MSR_K7_EVNTSEL2:

CRA Git | Maintained and supported by SUSTech CRA and CCSE