Commit 66fdb29d authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
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ARM: EXYNOS: Add a alias for pdma clocks 



PDMA controllers when instantiated from device tree are registered using
amba_device_register(). The registration process enables clock to the
controllers to read the peripheral id of the PDMA amba device.

In case of Exynos4, the clocks to the PDMA controllers are named as 'dma'
but amba_device_register() looks up the clock using the name 'apb_pclk'.
Hence, alias clocks with name 'apb_pclk' clock are created for clocks
with name 'dma'.

Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent fca3de6a

arch/arm/mach-exynos/clock.c

+25 −10
Original line number Diff line number Diff line
@@ -552,16 +552,6 @@ static struct clk init_clocks_off[] = { 
		.devname	= "s5p-sdo",

		.enable		= exynos4_clk_dac_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "dma",

		.devname	= "dma-pl330.0",

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "dma",

		.devname	= "dma-pl330.1",

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 1),

	}, {

		.name		= "adc",

		.enable		= exynos4_clk_ip_peril_ctrl,
@@ -778,6 +768,20 @@ static struct clk init_clocks[] = { 
	}

};



static struct clk clk_pdma0 = {

	.name		= "dma",

	.devname	= "dma-pl330.0",

	.enable		= exynos4_clk_ip_fsys_ctrl,

	.ctrlbit	= (1 << 0),

};



static struct clk clk_pdma1 = {

	.name		= "dma",

	.devname	= "dma-pl330.1",

	.enable		= exynos4_clk_ip_fsys_ctrl,

	.ctrlbit	= (1 << 1),

};



struct clk *clkset_group_list[] = {

	[0] = &clk_ext_xtal_mux,

	[1] = &clk_xusbxti,
@@ -1279,6 +1283,11 @@ static struct clksrc_clk *sysclks[] = { 
	&clk_mout_mfc1,

};



static struct clk *clk_cdev[] = {

	&clk_pdma0,

	&clk_pdma1,

};



static struct clksrc_clk *clksrc_cdev[] = {

	&clk_sclk_uart0,

	&clk_sclk_uart1,
@@ -1291,6 +1300,8 @@ static struct clk_lookup exynos4_clk_lookup[] = { 
	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),

	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),

	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),

	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),

	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),

};



static int xtal_rate;
@@ -1506,6 +1517,10 @@ void __init exynos4_register_clocks(void) 
	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));

	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));



	s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));

	for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)

		s3c_disable_clocks(clk_cdev[ptr], 1);



	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));

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