Commit 66f34aee authored by Hersen Wu's avatar Hersen Wu Committed by Alex Deucher
Browse files

drm/amd/display: RV2 DP MST 2nd display within daisy chain not light up



RV2 resource is limit to 3 pipes. Limitation should apply to all HW
blocks instead of front pipe.

Signed-off-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d567cc55
Loading
Loading
Loading
Loading
+18 −1
Original line number Diff line number Diff line
@@ -507,6 +507,18 @@ static const struct resource_caps res_cap = {
		.num_ddc = 4,
};

#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
static const struct resource_caps rv2_res_cap = {
		.num_timing_generator = 3,
		.num_opp = 3,
		.num_video_plane = 3,
		.num_audio = 3,
		.num_stream_encoder = 3,
		.num_pll = 3,
		.num_ddc = 3,
};
#endif

static const struct dc_debug_options debug_defaults_drv = {
		.sanity_checks = true,
		.disable_dmcu = true,
@@ -1172,6 +1184,11 @@ static bool construct(

	ctx->dc_bios->regs = &bios_regs;

#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
	if (ctx->dce_version == DCN_VERSION_1_01)
		pool->base.res_cap = &rv2_res_cap;
	else
#endif
		pool->base.res_cap = &res_cap;
	pool->base.funcs = &dcn10_res_pool_funcs;