gpio: mxs: Add IRQ_TYPE_EDGE_BOTH support (66d7990e) · Commits · 戴 / test

drivers/gpio/gpio-mxs.c

+31 −0

Original line number	Diff line number	Diff line
		@@ -65,6 +65,7 @@ struct mxs_gpio_port {
		struct irq_domain *domain;
		struct bgpio_chip bgc;
		enum mxs_gpio_id devid;
		u32 both_edges;
		};

		static inline int is_imx23_gpio(struct mxs_gpio_port *port)
		@@ -81,13 +82,23 @@ static inline int is_imx28_gpio(struct mxs_gpio_port *port)

		static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
		{
		u32 val;
		u32 pin_mask = 1 << d->hwirq;
		struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
		struct mxs_gpio_port *port = gc->private;
		void __iomem *pin_addr;
		int edge;

		port->both_edges &= ~pin_mask;
		switch (type) {
		case IRQ_TYPE_EDGE_BOTH:
		val = gpio_get_value(port->bgc.gc.base + d->hwirq);
		if (val)
		edge = GPIO_INT_FALL_EDGE;
		else
		edge = GPIO_INT_RISE_EDGE;
		port->both_edges \|= pin_mask;
		break;
		case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
		@@ -124,6 +135,23 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
		return 0;
		}

		static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
		{
		u32 bit, val, edge;
		void __iomem *pin_addr;

		bit = 1 << gpio;

		pin_addr = port->base + PINCTRL_IRQPOL(port);
		val = readl(pin_addr);
		edge = val & bit;

		if (edge)
		writel(bit, pin_addr + MXS_CLR);
		else
		writel(bit, pin_addr + MXS_SET);
		}

		/* MXS has one interrupt per gpio port */
		static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
		{
		@@ -137,6 +165,9 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)

		while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;
		if (port->both_edges & (1 << irqoffset))
		mxs_flip_edge(port, irqoffset);

		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
		irq_stat &= ~(1 << irqoffset);
		}

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