Commit 66c9457d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pwm/for-4.14-rc1' of... 

Merge tag 'pwm/for-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm updates from Thierry Reding:
 "The changes for this release include a new driver for the PWM
  controller found on SoCs of the ZTX ZX family. Support for an old
  SH-Mobile SoC has been dropped and the Rockchip and MediaTek drivers
  gain support for more generations.

  Other than that there are a bunch of coding style fixes, minor bug
  fixes and cleanup as well as documentation patches"

* tag 'pwm/for-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (32 commits)
  pwm: pwm-samsung: fix suspend/resume support
  pwm: samsung: Remove redundant checks from pwm_samsung_config()
  pwm: mediatek: Disable clock on PWM configuration failure
  dt-bindings: pwm: Add MT2712/MT7622 information
  pwm: mediatek: Fix clock control issue
  pwm: mediatek: Fix PWM source clock selection
  pwm: mediatek: Fix Kconfig description
  pwm: tegra: Explicitly request exclusive reset control
  pwm: hibvt: Explicitly request exclusive reset control
  pwm: tiehrpwm: Set driver data before runtime PM enable
  pwm: tiehrpwm: Miscellaneous coding style fixups
  pwm: tiecap: Set driver data before runtime PM enable
  pwm: tiecap: Miscellaneous coding style fixups
  dt-bindings: pwm: tiecap: Add TI 66AK2G SoC specific compatible
  pwm: tiehrpwm: fix clock imbalance in probe error path
  pwm: tiehrpwm: Fix runtime PM imbalance at unbind
  pwm: Kconfig: Enable pwm-tiecap to be built for Keystone
  pwm: Add ZTE ZX PWM device driver
  dt-bindings: pwm: Add bindings doc for ZTE ZX PWM controller
  pwm: bcm2835: Support for polarity setting via DT
  ...
parents 669bf77a 7755daf5

Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt

+2 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Required properties: 
- clocks: This clock defines the base clock frequency of the PWM hardware

  system, the period and the duty_cycle of the PWM signal is a multiple of

  the base period.

- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of

- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of

  the cells format.



Examples:
@@ -15,7 +15,7 @@ pwm@2020c000 { 
	compatible = "brcm,bcm2835-pwm";

	reg = <0x2020c000 0x28>;

	clocks = <&clk_pwm>;

	#pwm-cells = <2>;

	#pwm-cells = <3>;

};



clocks {

Documentation/devicetree/bindings/pwm/pwm-mediatek.txt

+5 −1
Original line number Diff line number Diff line
@@ -2,6 +2,8 @@ MediaTek PWM controller 


Required properties:

 - compatible: should be "mediatek,<name>-pwm":

   - "mediatek,mt2712-pwm": found on mt2712 SoC.

   - "mediatek,mt7622-pwm": found on mt7622 SoC.

   - "mediatek,mt7623-pwm": found on mt7623 SoC.

 - reg: physical base address and length of the controller's registers.

 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
@@ -10,7 +12,9 @@ Required properties: 
 - clock-names: must contain the following:

   - "top": the top clock generator

   - "main": clock used by the PWM core

   - "pwm1-5": the five per PWM clocks

   - "pwm1-8": the eight per PWM clocks for mt2712

   - "pwm1-6": the six per PWM clocks for mt7622

   - "pwm1-5": the five per PWM clocks for mt7623

 - pinctrl-names: Must contain a "default" entry.

 - pinctrl-0: One property must exist for each entry in pinctrl-names.

   See pinctrl/pinctrl-bindings.txt for details of the property values.

Documentation/devicetree/bindings/pwm/pwm-rockchip.txt

+9 −2
Original line number Diff line number Diff line
@@ -3,10 +3,17 @@ Rockchip PWM controller 
Required properties:

 - compatible: should be "rockchip,<name>-pwm"

   "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs

   "rockchip,rk3288-pwm": found on RK3288 SoC

   "rockchip,rk3288-pwm": found on RK3288 SOC

   "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC

   "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC

 - reg: physical base address and length of the controller's registers

 - clocks: phandle and clock specifier of the PWM reference clock

 - clocks: See ../clock/clock-bindings.txt

   - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):

     - There is one clock that's used both to derive the functional clock

       for the device and as the bus clock.

   - For newer hardware (rk3328 and future socs): specified by name

     - "pwm": This is used to derive the functional clock.

     - "pclk": This is the APB bus clock.

 - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory

   for a description of the cell format.

Documentation/devicetree/bindings/pwm/pwm-tiecap.txt

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ Required properties: 
  for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";

  for da850  - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";

  for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";

  for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap";

- #pwm-cells: should be 3. See pwm.txt in this directory for a description of

  the cells format. The PWM channel index ranges from 0 to 4. The only third

  cell flag supported by this binding is PWM_POLARITY_INVERTED.

Documentation/devicetree/bindings/pwm/pwm-zx.txt

0 → 100644
+22 −0
Original line number Diff line number Diff line 
ZTE ZX PWM controller



Required properties:

 - compatible: Should be "zte,zx296718-pwm".

 - reg: Physical base address and length of the controller's registers.

 - clocks : The phandle and specifier referencing the controller's clocks.

 - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller.  The

   PCLK is for register access, while WCLK is the reference clock for

   calculating period and duty cycles.

 - #pwm-cells: Should be 3. See pwm.txt in this directory for a description of

   the cells format.



Example:



	pwm: pwm@1439000 {

		compatible = "zte,zx296718-pwm";

		reg = <0x1439000 0x1000>;

		clocks = <&lsp1crm LSP1_PWM_PCLK>,

			 <&lsp1crm LSP1_PWM_WCLK>;

		clock-names = "pclk", "wclk";

		#pwm-cells = <3>;

	};

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