Commit 6694aee0 authored by Lars Povlsen's avatar Lars Povlsen Committed by Arnd Bergmann
Browse files

arm64: dts: sparx5: Add basic cpu support 

This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option).

Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com


Reviewed-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: default avatarLars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 31a91c87

MAINTAINERS

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@@ -2125,6 +2125,7 @@ M: Steen Hegelund <Steen.Hegelund@microchip.com> 
M:	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Supported

F:	arch/arm64/boot/dts/microchip/

N:	sparx5









ARM/MIOA701 MACHINE SUPPORT
































arch/arm64/boot/dts/Makefile



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@@ -17,6 +17,7 @@ subdir-y += intel







subdir-y += lg









subdir-y += marvell









subdir-y += mediatek









subdir-y += microchip









subdir-y += nvidia









subdir-y += qcom









subdir-y += realtek
































arch/arm64/boot/dts/microchip/Makefile
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# SPDX-License-Identifier: GPL-2.0









dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb









dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb









dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb
























arch/arm64/boot/dts/microchip/sparx5.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)









/*









 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.









 */



















#include <dt-bindings/gpio/gpio.h>









#include <dt-bindings/interrupt-controller/arm-gic.h>



















/ {









	compatible = "microchip,sparx5";









	interrupt-parent = <&gic>;









	#address-cells = <2>;









	#size-cells = <1>;



















	aliases {









		serial0 = &uart0;









		serial1 = &uart1;









	};



















	chosen {









		stdout-path = "serial0:115200n8";









	};



















	cpus {









		#address-cells = <2>;









		#size-cells = <0>;









		cpu-map {









			cluster0 {









				core0 {









					cpu = <&cpu0>;









				};









				core1 {









					cpu = <&cpu1>;









				};









			};









		};









		cpu0: cpu@0 {









			compatible = "arm,cortex-a53";









			device_type = "cpu";









			reg = <0x0 0x0>;









			enable-method = "psci";









			next-level-cache = <&L2_0>;









		};









		cpu1: cpu@1 {









			compatible = "arm,cortex-a53";









			device_type = "cpu";









			reg = <0x0 0x1>;









			enable-method = "psci";









			next-level-cache = <&L2_0>;









		};









		L2_0: l2-cache0 {









			compatible = "cache";









		};









	};



















	arm-pmu {









		compatible = "arm,cortex-a53-pmu";









		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;









		interrupt-affinity = <&cpu0>, <&cpu1>;









	};



















	psci {









		compatible = "arm,psci-0.2";









		method = "smc";









	};



















	timer {









		compatible = "arm,armv8-timer";









		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,









			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,









			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,









			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;









	};



















	clocks: clocks {









		#address-cells = <2>;









		#size-cells = <1>;









		ranges;









		ahb_clk: ahb-clk {









			compatible = "fixed-clock";









			#clock-cells = <0>;









			clock-frequency = <250000000>;









		};









		sys_clk: sys-clk {









			compatible = "fixed-clock";









			#clock-cells = <0>;









			clock-frequency = <625000000>;









		};









	};



















	axi: axi@600000000 {









		compatible = "simple-bus";









		#address-cells = <2>;









		#size-cells = <1>;









		ranges;



















		gic: interrupt-controller@600300000 {









			compatible = "arm,gic-v3";









			#interrupt-cells = <3>;









			#address-cells = <2>;









			#size-cells = <2>;









			interrupt-controller;









			reg = <0x6 0x00300000 0x10000>,	/* GIC Dist */









			      <0x6 0x00340000 0xc0000>,	/* GICR */









			      <0x6 0x00200000 0x2000>,	/* GICC */









			      <0x6 0x00210000 0x2000>,  /* GICV */









			      <0x6 0x00220000 0x2000>;  /* GICH */









			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;









		};



















		uart0: serial@600100000 {









			compatible = "ns16550a";









			reg = <0x6 0x00100000 0x20>;









			clocks = <&ahb_clk>;









			reg-io-width = <4>;









			reg-shift = <2>;









			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;



















			status = "disabled";









		};



















		uart1: serial@600102000 {









			compatible = "ns16550a";









			reg = <0x6 0x00102000 0x20>;









			clocks = <&ahb_clk>;









			reg-io-width = <4>;









			reg-shift = <2>;









			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;



















			status = "disabled";









		};



















		timer1: timer@600105000 {









			compatible = "snps,dw-apb-timer";









			reg = <0x6 0x00105000 0x1000>;









			clocks = <&ahb_clk>;









			clock-names = "timer";









			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;









		};



















	};









};
























arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)









/*









 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.









 */



















/dts-v1/;









#include "sparx5_pcb_common.dtsi"



















/ {









	model = "Sparx5 PCB125 Reference Board";









	compatible = "microchip,sparx5-pcb125", "microchip,sparx5";



















	memory@0 {









		device_type = "memory";









		reg = <0x00000000 0x00000000 0x10000000>;









	};









};
































































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