Commit 6677c3b1 authored Sep 24, 2019 by José Roberto de Souza

drm/i915/tgl: Return the mg/dkl pll as DDI clock for new TC ports



TGL added 2 more TC ports that currently are not being handled by
icl_pll_to_ddi_clk_sel(), so adding those.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reported-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190924210040.142075-6-jose.souza@intel.com

parent ee7de6ad

drivers/gpu/drm/i915/display/intel_ddi.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -1049,6 +1049,8 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
		case DPLL_ID_ICL_MGPLL2:
		case DPLL_ID_ICL_MGPLL3:
		case DPLL_ID_ICL_MGPLL4:
		case DPLL_ID_TGL_MGPLL5:
		case DPLL_ID_TGL_MGPLL6:
		return DDI_CLK_SEL_MG;
		}
		}

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