Commit 65cdc405 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-fixes-v4.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU fixes from Joerg Roedel:
 "Three fixes queued up:

   - fix an issue with command buffer overflow handling in the AMD IOMMU
     driver

   - add an additional context entry flush to the Intel VT-d driver to
     make sure any old context entry from kdump copying is flushed out
     of the cache

   - correct the encoding of the PASID table size in the Intel VT-d
     driver"

* tag 'iommu-fixes-v4.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  iommu/amd: Fix the left value check of cmd buffer
  iommu/vt-d: Fix pasid table size encoding
  iommu/vt-d: Flush old iommu caches for kdump when the device gets context mapped
parents 7397e1e8 432abf68

drivers/iommu/amd_iommu.c

+1 −1
Original line number Diff line number Diff line
@@ -1023,7 +1023,7 @@ again: 
	next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;

	left      = (head - next_tail) % CMD_BUFFER_SIZE;



	if (left <= 2) {

	if (left <= 0x20) {

		struct iommu_cmd sync_cmd;

		int ret;

drivers/iommu/intel-iommu.c

+41 −1
Original line number Diff line number Diff line
@@ -2037,6 +2037,25 @@ static int domain_context_mapping_one(struct dmar_domain *domain, 
	if (context_present(context))

		goto out_unlock;



	/*

	 * For kdump cases, old valid entries may be cached due to the

	 * in-flight DMA and copied pgtable, but there is no unmapping

	 * behaviour for them, thus we need an explicit cache flush for

	 * the newly-mapped device. For kdump, at this point, the device

	 * is supposed to finish reset at its driver probe stage, so no

	 * in-flight DMA will exist, and we don't need to worry anymore

	 * hereafter.

	 */

	if (context_copied(context)) {

		u16 did_old = context_domain_id(context);



		if (did_old >= 0 && did_old < cap_ndoms(iommu->cap))

			iommu->flush.flush_context(iommu, did_old,

						   (((u16)bus) << 8) | devfn,

						   DMA_CCMD_MASK_NOBIT,

						   DMA_CCMD_DEVICE_INVL);

	}



	pgd = domain->pgd;



	context_clear_entry(context);
@@ -5185,6 +5204,25 @@ static void intel_iommu_remove_device(struct device *dev) 
}



#ifdef CONFIG_INTEL_IOMMU_SVM

#define MAX_NR_PASID_BITS (20)

static inline unsigned long intel_iommu_get_pts(struct intel_iommu *iommu)

{

	/*

	 * Convert ecap_pss to extend context entry pts encoding, also

	 * respect the soft pasid_max value set by the iommu.

	 * - number of PASID bits = ecap_pss + 1

	 * - number of PASID table entries = 2^(pts + 5)

	 * Therefore, pts = ecap_pss - 4

	 * e.g. KBL ecap_pss = 0x13, PASID has 20 bits, pts = 15

	 */

	if (ecap_pss(iommu->ecap) < 5)

		return 0;



	/* pasid_max is encoded as actual number of entries not the bits */

	return find_first_bit((unsigned long *)&iommu->pasid_max,

			MAX_NR_PASID_BITS) - 5;

}



int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev)

{

	struct device_domain_info *info;
@@ -5217,7 +5255,9 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sd 


	if (!(ctx_lo & CONTEXT_PASIDE)) {

		context[1].hi = (u64)virt_to_phys(iommu->pasid_state_table);

		context[1].lo = (u64)virt_to_phys(iommu->pasid_table) | ecap_pss(iommu->ecap);

		context[1].lo = (u64)virt_to_phys(iommu->pasid_table) |

			intel_iommu_get_pts(iommu);



		wmb();

		/* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB are both

		 * extended to permit requests-with-PASID if the PASIDE bit

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