Commit 65beea4c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-5.1-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:
 "A few minor fixes for ARC.

   - regression in memset if line size !64

   - avoid panic if PAE and IOC"

* tag 'arc-5.1-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: memset: fix build with L1_CACHE_SHIFT != 6
  ARC: [hsdk] Make it easier to add PAE40 region to DTB
  ARC: PAE40: don't panic and instead turn off hw ioc
parents fb0af61d 55c0c4c7

arch/arc/boot/dts/hsdk.dts

+7 −6
Original line number Diff line number Diff line
@@ -18,8 +18,8 @@ 
	model = "snps,hsdk";

	compatible = "snps,hsdk";



	#address-cells = <1>;

	#size-cells = <1>;

	#address-cells = <2>;

	#size-cells = <2>;



	chosen {

		bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
@@ -105,7 +105,7 @@ 
		#size-cells = <1>;

		interrupt-parent = <&idu_intc>;



		ranges = <0x00000000 0xf0000000 0x10000000>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;



		cgu_rst: reset-controller@8a0 {

			compatible = "snps,hsdk-reset";
@@ -269,9 +269,10 @@ 
	};



	memory@80000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		#address-cells = <2>;

		#size-cells = <2>;

		device_type = "memory";

		reg = <0x80000000 0x40000000>;  /* 1 GiB */

		reg = <0x0 0x80000000 0x0 0x40000000>;  /* 1 GB lowmem */

		/*     0x1 0x00000000 0x0 0x40000000>;     1 GB highmem */

	};

};

arch/arc/lib/memset-archs.S

+2 −2
Original line number Diff line number Diff line
@@ -30,10 +30,10 @@ 


#else



.macro PREALLOC_INSTR

.macro PREALLOC_INSTR	reg, off

.endm



.macro PREFETCHW_INSTR

.macro PREFETCHW_INSTR	reg, off

.endm



#endif

arch/arc/mm/cache.c

+16 −15
Original line number Diff line number Diff line
@@ -113,10 +113,24 @@ static void read_decode_cache_bcr_arcv2(int cpu) 
	}



	READ_BCR(ARC_REG_CLUSTER_BCR, cbcr);

	if (cbcr.c)

	if (cbcr.c) {

		ioc_exists = 1;

	else



		/*

		 * As for today we don't support both IOC and ZONE_HIGHMEM enabled

		 * simultaneously. This happens because as of today IOC aperture covers

		 * only ZONE_NORMAL (low mem) and any dma transactions outside this

		 * region won't be HW coherent.

		 * If we want to use both IOC and ZONE_HIGHMEM we can use

		 * bounce_buffer to handle dma transactions to HIGHMEM.

		 * Also it is possible to modify dma_direct cache ops or increase IOC

		 * aperture size if we are planning to use HIGHMEM without PAE.

		 */

		if (IS_ENABLED(CONFIG_HIGHMEM) || is_pae40_enabled())

			ioc_enable = 0;

	} else {

		ioc_enable = 0;

	}



	/* HS 2.0 didn't have AUX_VOL */

	if (cpuinfo_arc700[cpu].core.family > 0x51) {
@@ -1158,19 +1172,6 @@ noinline void __init arc_ioc_setup(void) 
	if (!ioc_enable)

		return;



	/*

	 * As for today we don't support both IOC and ZONE_HIGHMEM enabled

	 * simultaneously. This happens because as of today IOC aperture covers

	 * only ZONE_NORMAL (low mem) and any dma transactions outside this

	 * region won't be HW coherent.

	 * If we want to use both IOC and ZONE_HIGHMEM we can use

	 * bounce_buffer to handle dma transactions to HIGHMEM.

	 * Also it is possible to modify dma_direct cache ops or increase IOC

	 * aperture size if we are planning to use HIGHMEM without PAE.

	 */

	if (IS_ENABLED(CONFIG_HIGHMEM))

		panic("IOC and HIGHMEM can't be used simultaneously");



	/* Flush + invalidate + disable L1 dcache */

	__dc_disable();

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