Commit 65ae8d26 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Ralf Baechle
Browse files

MIPS16e2: Provide feature overrides for non-MIPS16 systems



Hardcode the absence of the MIPS16e2 ASE for all the systems that do so
for the MIPS16 ASE already, providing for code to be optimized away.

Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16097/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 92ecd19a
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Original line number Diff line number Diff line
@@ -40,6 +40,7 @@
#endif

#define cpu_has_mips16			0
#define cpu_has_mips16e2		0
#define cpu_has_mdmx			0
#define cpu_has_mips3d			0
#define cpu_has_smartmips		0
+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@
#define cpu_has_ejtag			1
#define cpu_has_llsc			1
#define cpu_has_mips16			0
#define cpu_has_mips16e2		0
#define cpu_has_mdmx			0
#define cpu_has_mips3d			0
#define cpu_has_smartmips		0
+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@
#define cpu_has_ejtag			1
#define cpu_has_llsc			1
#define cpu_has_mips16			0
#define cpu_has_mips16e2		0
#define cpu_has_mdmx			0
#define cpu_has_mips3d			0
#define cpu_has_smartmips		0
+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@
#endif

#define cpu_has_mips16		0
#define cpu_has_mips16e2	0
#define cpu_has_mdmx		0
#define cpu_has_mips3d		0
#define cpu_has_smartmips	0
+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@
#define cpu_has_mcheck			0
#define cpu_has_ejtag			0
#define cpu_has_mips16			0
#define cpu_has_mips16e2		0
#define cpu_has_mdmx			0
#define cpu_has_mips3d			0
#define cpu_has_smartmips		0
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