scsi: hisi_sas: Set the BIST init value before enabling BIST (65a3b8bd) · Commits · 戴 / test

If set the BIST init value after enabling BIST, there may be still some few error bits. According to the process, need to set the BIST init value before enabling BIST. Fixes: ("scsi: hisi_sas: Add BIST support for phy loopback") Link: https://lore.kernel.org/r/1571926105-74636-3-git-send-email-john.garry@huawei.com Signed-off-by:

Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by:

John Garry <john.garry@huawei.com> Signed-off-by:

Martin K. Petersen <martin.petersen@oracle.com>

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

+5 −5

Original line number	Diff line number	Diff line
		@@ -3022,11 +3022,6 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
		hisi_sas_phy_write32(hisi_hba, phy_id,
		SAS_PHY_BIST_CTRL, reg_val);

		mdelay(100);
		reg_val \|= (CFG_RX_BIST_EN_MSK \| CFG_TX_BIST_EN_MSK);
		hisi_sas_phy_write32(hisi_hba, phy_id,
		SAS_PHY_BIST_CTRL, reg_val);

		/* set the bist init value */
		hisi_sas_phy_write32(hisi_hba, phy_id,
		SAS_PHY_BIST_CODE,
		@@ -3035,6 +3030,11 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
		SAS_PHY_BIST_CODE1,
		SAS_PHY_BIST_CODE1_INIT);

		mdelay(100);
		reg_val \|= (CFG_RX_BIST_EN_MSK \| CFG_TX_BIST_EN_MSK);
		hisi_sas_phy_write32(hisi_hba, phy_id,
		SAS_PHY_BIST_CTRL, reg_val);

		/* clear error bit */
		mdelay(100);
		hisi_sas_phy_read32(hisi_hba, phy_id, SAS_BIST_ERR_CNT);

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