Unverified Commit 658a731c authored by Maxime Ripard's avatar Maxime Ripard
Browse files

drm/vc4: crtc: Add BCM2711 pixelvalves 



The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add
support for them.

Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Tested-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Tested-by: default avatarHoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/2553ec9ece0d8a0e5299ff74ed932a38703c5db9.1599120059.git-series.maxime@cerno.tech
parent 2ed19897

drivers/gpu/drm/vc4/vc4_crtc.c

+93 −2
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ void vc4_crtc_destroy(struct drm_crtc *crtc) 


static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)

{

	const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);

	const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);

	u32 fifo_len_bytes = pv_data->fifo_depth;
@@ -230,6 +231,13 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) 
	case PV_CONTROL_FORMAT_24:

	case PV_CONTROL_FORMAT_DSIV_24:

	default:

		/*

		 * For some reason, the pixelvalve4 doesn't work with

		 * the usual formula and will only work with 32.

		 */

		if (crtc_data->hvs_output == 5)

			return 32;



		return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;

	}

}
@@ -238,8 +246,12 @@ static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc, 
					     u32 format)

{

	u32 level = vc4_get_fifo_full_level(vc4_crtc, format);

	u32 ret = 0;



	ret |= VC4_SET_FIELD((level >> 6),

			     PV5_CONTROL_FIFO_LEVEL_HIGH);



	return VC4_SET_FIELD(level & 0x3f,

	return ret | VC4_SET_FIELD(level & 0x3f,

				   PV_CONTROL_FIFO_LEVEL);

}
@@ -278,6 +290,8 @@ static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc) 


static void vc4_crtc_config_pv(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);

	struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);

	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
@@ -358,6 +372,11 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) 
	if (is_dsi)

		CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);



	if (vc4->hvs->hvs5)

		CRTC_WRITE(PV_MUX_CFG,

			   VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,

					 PV_MUX_CFG_RGB_PIXEL_MUX_MODE));



	CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |

		   vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |

		   VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
@@ -907,10 +926,82 @@ static const struct vc4_pv_data bcm2835_pv2_data = { 
	},

};



static const struct vc4_pv_data bcm2711_pv0_data = {

	.base = {

		.hvs_available_channels = BIT(0),

		.hvs_output = 0,

	},

	.debugfs_name = "crtc0_regs",

	.fifo_depth = 64,

	.pixels_per_clock = 1,

	.encoder_types = {

		[0] = VC4_ENCODER_TYPE_DSI0,

		[1] = VC4_ENCODER_TYPE_DPI,

	},

};



static const struct vc4_pv_data bcm2711_pv1_data = {

	.base = {

		.hvs_available_channels = BIT(0) | BIT(1) | BIT(2),

		.hvs_output = 3,

	},

	.debugfs_name = "crtc1_regs",

	.fifo_depth = 64,

	.pixels_per_clock = 1,

	.encoder_types = {

		[0] = VC4_ENCODER_TYPE_DSI1,

		[1] = VC4_ENCODER_TYPE_SMI,

	},

};



static const struct vc4_pv_data bcm2711_pv2_data = {

	.base = {

		.hvs_available_channels = BIT(0) | BIT(1) | BIT(2),

		.hvs_output = 4,

	},

	.debugfs_name = "crtc2_regs",

	.fifo_depth = 256,

	.pixels_per_clock = 2,

	.encoder_types = {

		[0] = VC4_ENCODER_TYPE_HDMI0,

	},

};



static const struct vc4_pv_data bcm2711_pv3_data = {

	.base = {

		.hvs_available_channels = BIT(1),

		.hvs_output = 1,

	},

	.debugfs_name = "crtc3_regs",

	.fifo_depth = 64,

	.pixels_per_clock = 1,

	.encoder_types = {

		[0] = VC4_ENCODER_TYPE_VEC,

	},

};



static const struct vc4_pv_data bcm2711_pv4_data = {

	.base = {

		.hvs_available_channels = BIT(0) | BIT(1) | BIT(2),

		.hvs_output = 5,

	},

	.debugfs_name = "crtc4_regs",

	.fifo_depth = 64,

	.pixels_per_clock = 2,

	.encoder_types = {

		[0] = VC4_ENCODER_TYPE_HDMI1,

	},

};



static const struct of_device_id vc4_crtc_dt_match[] = {

	{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },

	{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },

	{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },

	{ .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },

	{ .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },

	{ .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },

	{ .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },

	{ .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },

	{}

};

drivers/gpu/drm/vc4/vc4_regs.h

+7 −0
Original line number Diff line number Diff line
@@ -129,6 +129,8 @@ 
#define V3D_ERRSTAT  0x00f20



#define PV_CONTROL				0x00

# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK	VC4_MASK(26, 25)

# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT	25

# define PV_CONTROL_FORMAT_MASK			VC4_MASK(23, 21)

# define PV_CONTROL_FORMAT_SHIFT		21

# define PV_CONTROL_FORMAT_24			0
@@ -208,6 +210,11 @@ 


#define PV_HACT_ACT				0x30



#define PV_MUX_CFG				0x34

# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK	VC4_MASK(5, 2)

# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT	2

# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP	8



#define SCALER_CHANNELS_COUNT			3



#define SCALER_DISPCTRL                         0x00000000

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