Commit 65887291 authored by Oded Gabbay's avatar Oded Gabbay
Browse files

habanalabs: use FIELD_PREP() instead of << 



Use the standard FIELD_PREP() macro instead of << operator to perform
bitmask operations. This ensures type check safety and eliminate compiler
warnings.

Reported-by: default avatarkernel test robot <lkp@intel.com>
Reviewed-by: default avatarTomer Tayar <ttayar@habana.ai>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent a0e072f5

drivers/misc/habanalabs/common/hw_queue.c

+5 −4
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include "habanalabs.h"



#include <linux/slab.h>

#include <linux/bitfield.h>



/*

 * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
@@ -290,8 +291,8 @@ static void ext_queue_schedule_job(struct hl_cs_job *job) 
	cq_pkt.data = cpu_to_le32(

			((q->pi << CQ_ENTRY_SHADOW_INDEX_SHIFT)

				& CQ_ENTRY_SHADOW_INDEX_MASK) |

				(1 << CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT) |

				(1 << CQ_ENTRY_READY_SHIFT));

			FIELD_PREP(CQ_ENTRY_SHADOW_INDEX_VALID_MASK, 1) |

			FIELD_PREP(CQ_ENTRY_READY_MASK, 1));



	/*

	 * No need to protect pi_offset because scheduling to the

drivers/misc/habanalabs/gaudi/gaudi.c

+27 −23
Original line number Diff line number Diff line
@@ -682,10 +682,10 @@ static int _gaudi_init_tpc_mem(struct hl_device *hdev, 


	init_tpc_mem_pkt->tsize = cpu_to_le32(tpc_kernel_size);



	ctl = ((PACKET_LIN_DMA << GAUDI_PKT_CTL_OPCODE_SHIFT) |

			(1 << GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT) |

			(1 << GAUDI_PKT_CTL_RB_SHIFT) |

			(1 << GAUDI_PKT_CTL_MB_SHIFT));

	ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA);

	ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_LIN_MASK, 1);

	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);

	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);



	init_tpc_mem_pkt->ctl = cpu_to_le32(ctl);
@@ -2328,7 +2328,8 @@ static void gaudi_init_tpc_qmans(struct hl_device *hdev) 


		tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0;



		gaudi->hw_cap_initialized |= 1 << (HW_CAP_TPC_SHIFT + tpc_id);

		gaudi->hw_cap_initialized |=

				FIELD_PREP(HW_CAP_TPC_MASK, 1 << tpc_id);

	}

}
@@ -2907,13 +2908,13 @@ static void gaudi_pre_hw_init(struct hl_device *hdev) 
					(CFG_RST_H_DMA_MASK |

					CFG_RST_H_MME_MASK |

					CFG_RST_H_SM_MASK |

					CFG_RST_H_TPC_MASK));

					CFG_RST_H_TPC_7_MASK));



	WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK);



	WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H,

					(CFG_RST_H_HBM_MASK |

					CFG_RST_H_TPC_MASK |

					CFG_RST_H_TPC_7_MASK |

					CFG_RST_H_NIC_MASK |

					CFG_RST_H_SM_MASK |

					CFG_RST_H_DMA_MASK |
@@ -3466,9 +3467,10 @@ static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) 
		goto free_fence_ptr;

	}



	tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) |

			(1 << GAUDI_PKT_CTL_EB_SHIFT) |

			(1 << GAUDI_PKT_CTL_MB_SHIFT);

	tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);

	tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);

	tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);



	fence_pkt->ctl = cpu_to_le32(tmp);

	fence_pkt->value = cpu_to_le32(fence_val);

	fence_pkt->addr = cpu_to_le64(fence_dma_addr);
@@ -4285,11 +4287,11 @@ static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, 
	cq_pkt = (struct packet_msg_prot *) (uintptr_t)

		(kernel_address + len - (sizeof(struct packet_msg_prot) * 2));



	tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) |

			(1 << GAUDI_PKT_CTL_MB_SHIFT);

	tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);

	tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);



	if (eb)

		tmp |= (1 << GAUDI_PKT_CTL_EB_SHIFT);

		tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);



	cq_pkt->ctl = cpu_to_le32(tmp);

	cq_pkt->value = cpu_to_le32(cq_val);
@@ -4297,8 +4299,8 @@ static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, 


	cq_pkt++;



	tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) |

			(1 << GAUDI_PKT_CTL_MB_SHIFT);

	tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);

	tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);

	cq_pkt->ctl = cpu_to_le32(tmp);

	cq_pkt->value = cpu_to_le32(1);
@@ -4330,11 +4332,12 @@ static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, 
	memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));

	cb_size = sizeof(*lin_dma_pkt);



	ctl = ((PACKET_LIN_DMA << GAUDI_PKT_CTL_OPCODE_SHIFT) |

			(1 << GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |

			(1 << GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT) |

			(1 << GAUDI_PKT_CTL_RB_SHIFT) |

			(1 << GAUDI_PKT_CTL_MB_SHIFT));

	ctl = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_LIN_DMA);

	ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK, 1);

	ctl |= FIELD_PREP(GAUDI_PKT_LIN_DMA_CTL_LIN_MASK, 1);

	ctl |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);

	ctl |= FIELD_PREP(GAUDI_PKT_CTL_RB_MASK, 1);



	lin_dma_pkt->ctl = cpu_to_le32(ctl);

	lin_dma_pkt->src_addr = cpu_to_le64(val);

	lin_dma_pkt->dst_addr |= cpu_to_le64(addr);
@@ -4940,9 +4943,10 @@ static int gaudi_send_job_on_qman0(struct hl_device *hdev, 
	fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address +

			job->job_cb_size - sizeof(struct packet_msg_prot));



	tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) |

			(1 << GAUDI_PKT_CTL_EB_SHIFT) |

			(1 << GAUDI_PKT_CTL_MB_SHIFT);

	tmp = FIELD_PREP(GAUDI_PKT_CTL_OPCODE_MASK, PACKET_MSG_PROT);

	tmp |= FIELD_PREP(GAUDI_PKT_CTL_EB_MASK, 1);

	tmp |= FIELD_PREP(GAUDI_PKT_CTL_MB_MASK, 1);



	fence_pkt->ctl = cpu_to_le32(tmp);

	fence_pkt->value = cpu_to_le32(GAUDI_QMAN0_FENCE_VAL);

	fence_pkt->addr = cpu_to_le64(fence_dma_addr);

drivers/misc/habanalabs/include/gaudi/gaudi_masks.h

+122 −152
Original line number Diff line number Diff line
@@ -9,194 +9,164 @@ 
#define GAUDI_MASKS_H_



#include "asic_reg/gaudi_regs.h"

#include <linux/bitfield.h>



/* Useful masks for bits in various registers */

#define PCI_DMA_QMAN_ENABLE		(\

	(0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \

	(0xF << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \

	(0xF << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT))

	(FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))



#define QMAN_EXTERNAL_MAKE_TRUSTED	(\

	(0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \

	(0xF << DMA0_QM_GLBL_PROT_CQF_SHIFT) | \

	(0xF << DMA0_QM_GLBL_PROT_CP_SHIFT) | \

	(0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT))

	(FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))



#define QMAN_INTERNAL_MAKE_TRUSTED	(\

	(0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \

	(0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT))

	(FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))



#define HBM_DMA_QMAN_ENABLE		(\

	(0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \

	(0x1F << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \

	(0x1F << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT))

	(FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \

	(FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))



#define QMAN_MME_ENABLE		(\

	(0xF << MME0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \

	(0x1F << MME0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \

	(0x1F << MME0_QM_GLBL_CFG0_CP_EN_SHIFT))

	(FIELD_PREP(MME0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \

	(FIELD_PREP(MME0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \

	(FIELD_PREP(MME0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))



#define QMAN_TPC_ENABLE		(\

	(0xF << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \

	(0x1F << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \

	(0x1F << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT))

	(FIELD_PREP(TPC0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \

	(FIELD_PREP(TPC0_QM_GLBL_CFG0_CQF_EN_MASK, 0x1F)) | \

	(FIELD_PREP(TPC0_QM_GLBL_CFG0_CP_EN_MASK, 0x1F)))



#define QMAN_UPPER_CP_CGM_PWR_GATE_EN	(\

	(0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \

	(0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \

	(0x10 << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \

	(1 << DMA0_QM_CGM_CFG_EN_SHIFT))

	(FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \

	(FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \

	(FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0x10)) | \

	(FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))



#define QMAN_COMMON_CP_CGM_PWR_GATE_EN	(\

	(0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \

	(0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \

	(0xF << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \

	(1 << DMA0_QM_CGM_CFG_EN_SHIFT))

	(FIELD_PREP(DMA0_QM_CGM_CFG_IDLE_TH_MASK, 0x20)) | \

	(FIELD_PREP(DMA0_QM_CGM_CFG_G2F_TH_MASK, 0xA)) | \

	(FIELD_PREP(DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))



#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\

	(0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \

	(0xF << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \

	(0xF << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0xF)))



#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\

	(0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \

	(0xF << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \

	(0xF << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0xF)))



#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\

	(0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \

	(0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \

	(0x1F << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))



#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\

	(0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \

	(0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \

	(0x1F << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \

	(FIELD_PREP(DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))



#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\

	(0xF << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \

	(0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \

	(0x1F << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))

	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \

	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \

	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))



#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\

	(0xF << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \

	(0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \

	(0x1F << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))

	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \

	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \

	(FIELD_PREP(TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))



#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK	(\

	(0xF << MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \

	(0x1F << MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \

	(0x1F << MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT))

	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK, 0xF)) | \

	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK, 0x1F)) | \

	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK, 0x1F)))



#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK	(\

	(0xF << MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \

	(0x1F << MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \

	(0x1F << MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))

	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK, 0xF)) | \

	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK, 0x1F)) | \

	(FIELD_PREP(MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK, 0x1F)))



#define QMAN_CGM1_PWR_GATE_EN	(0xA << DMA0_QM_CGM_CFG1_MASK_TH_SHIFT)

#define QMAN_CGM1_PWR_GATE_EN	(FIELD_PREP(DMA0_QM_CGM_CFG1_MASK_TH_MASK, 0xA))



/* RESET registers configuration */

#define CFG_RST_L_PSOC_SHIFT		0

#define CFG_RST_L_PCIE_SHIFT		1

#define CFG_RST_L_PCIE_IF_SHIFT		2

#define CFG_RST_L_HBM_S_PLL_SHIFT	3

#define CFG_RST_L_TPC_S_PLL_SHIFT	4

#define CFG_RST_L_MME_S_PLL_SHIFT	5

#define CFG_RST_L_CPU_PLL_SHIFT		6

#define CFG_RST_L_PCIE_PLL_SHIFT	7

#define CFG_RST_L_NIC_S_PLL_SHIFT	8

#define CFG_RST_L_HBM_N_PLL_SHIFT	9

#define CFG_RST_L_TPC_N_PLL_SHIFT	10

#define CFG_RST_L_MME_N_PLL_SHIFT	11

#define CFG_RST_L_NIC_N_PLL_SHIFT	12

#define CFG_RST_L_DMA_W_PLL_SHIFT	13

#define CFG_RST_L_SIF_W_PLL_SHIFT	14

#define CFG_RST_L_MESH_W_PLL_SHIFT	15

#define CFG_RST_L_SRAM_W_PLL_SHIFT	16

#define CFG_RST_L_DMA_E_PLL_SHIFT	17

#define CFG_RST_L_SIF_E_PLL_SHIFT	18

#define CFG_RST_L_MESH_E_PLL_SHIFT	19

#define CFG_RST_L_SRAM_E_PLL_SHIFT	20

#define CFG_RST_L_IF_1_SHIFT		21

#define CFG_RST_L_IF_0_SHIFT		22

#define CFG_RST_L_IF_2_SHIFT		23

#define CFG_RST_L_IF_3_SHIFT		24

#define CFG_RST_L_TPC_0_SHIFT		25

#define CFG_RST_L_TPC_1_SHIFT		26

#define CFG_RST_L_TPC_2_SHIFT		27

#define CFG_RST_L_TPC_3_SHIFT		28

#define CFG_RST_L_TPC_4_SHIFT		29

#define CFG_RST_L_TPC_5_SHIFT		30

#define CFG_RST_L_TPC_6_SHIFT		31

#define CFG_RST_H_TPC_7_SHIFT		0

#define CFG_RST_H_MME_0_SHIFT		1

#define CFG_RST_H_MME_1_SHIFT		2

#define CFG_RST_H_MME_2_SHIFT		3

#define CFG_RST_H_MME_3_SHIFT		4

#define CFG_RST_H_HBM_0_SHIFT		5

#define CFG_RST_H_HBM_1_SHIFT		6

#define CFG_RST_H_HBM_2_SHIFT		7

#define CFG_RST_H_HBM_3_SHIFT		8

#define CFG_RST_H_NIC_0_SHIFT		9

#define CFG_RST_H_NIC_1_SHIFT		10

#define CFG_RST_H_NIC_2_SHIFT		11

#define CFG_RST_H_NIC_3_SHIFT		12

#define CFG_RST_H_NIC_4_SHIFT		13

#define CFG_RST_H_SM_0_SHIFT		14

#define CFG_RST_H_SM_1_SHIFT		15

#define CFG_RST_H_SM_2_SHIFT		16

#define CFG_RST_H_SM_3_SHIFT		17

#define CFG_RST_H_DMA_0_SHIFT		18

#define CFG_RST_H_DMA_1_SHIFT		19

#define CFG_RST_H_CPU_SHIFT		20

#define CFG_RST_H_MMU_SHIFT		21





#define CFG_RST_H_DMA_MASK		((1 << CFG_RST_H_DMA_0_SHIFT) | \

					(1 << CFG_RST_H_DMA_1_SHIFT))



#define CFG_RST_H_CPU_MASK		(1 << CFG_RST_H_CPU_SHIFT)

#define CFG_RST_H_MMU_MASK		(1 << CFG_RST_H_MMU_SHIFT)



#define CFG_RST_H_HBM_MASK		((1 << CFG_RST_H_HBM_0_SHIFT) | \

					(1 << CFG_RST_H_HBM_1_SHIFT) | \

					(1 << CFG_RST_H_HBM_2_SHIFT) | \

					(1 << CFG_RST_H_HBM_3_SHIFT))



#define CFG_RST_H_NIC_MASK		((1 << CFG_RST_H_NIC_0_SHIFT) | \

					(1 << CFG_RST_H_NIC_1_SHIFT) | \

					(1 << CFG_RST_H_NIC_2_SHIFT) | \

					(1 << CFG_RST_H_NIC_3_SHIFT) | \

					(1 << CFG_RST_H_NIC_4_SHIFT))



#define CFG_RST_H_SM_MASK		((1 << CFG_RST_H_SM_0_SHIFT) | \

					(1 << CFG_RST_H_SM_1_SHIFT) | \

					(1 << CFG_RST_H_SM_2_SHIFT) | \

					(1 << CFG_RST_H_SM_3_SHIFT))



#define CFG_RST_H_MME_MASK		((1 << CFG_RST_H_MME_0_SHIFT) | \

					(1 << CFG_RST_H_MME_1_SHIFT) | \

					(1 << CFG_RST_H_MME_2_SHIFT) | \

					(1 << CFG_RST_H_MME_3_SHIFT))



#define CFG_RST_L_PSOC_MASK		(1 << CFG_RST_L_PSOC_SHIFT)



#define CFG_RST_L_IF_MASK		((1 << CFG_RST_L_IF_0_SHIFT) | \

					(1 << CFG_RST_L_IF_1_SHIFT) | \

					(1 << CFG_RST_L_IF_2_SHIFT) | \

					(1 << CFG_RST_L_IF_3_SHIFT))



#define CFG_RST_L_TPC_MASK		((1 << CFG_RST_L_TPC_0_SHIFT) | \

					(1 << CFG_RST_L_TPC_1_SHIFT) | \

					(1 << CFG_RST_L_TPC_2_SHIFT) | \

					(1 << CFG_RST_L_TPC_3_SHIFT) | \

					(1 << CFG_RST_L_TPC_4_SHIFT) | \

					(1 << CFG_RST_L_TPC_5_SHIFT) | \

					(1 << CFG_RST_L_TPC_6_SHIFT))



#define CFG_RST_H_TPC_MASK		(1 << CFG_RST_H_TPC_7_SHIFT)



#define CA53_RESET			(1 << CFG_RST_H_CPU_SHIFT)

#define CFG_RST_L_PSOC_MASK		BIT_MASK(0)

#define CFG_RST_L_PCIE_MASK		BIT_MASK(1)

#define CFG_RST_L_PCIE_IF_MASK		BIT_MASK(2)

#define CFG_RST_L_HBM_S_PLL_MASK	BIT_MASK(3)

#define CFG_RST_L_TPC_S_PLL_MASK	BIT_MASK(4)

#define CFG_RST_L_MME_S_PLL_MASK	BIT_MASK(5)

#define CFG_RST_L_CPU_PLL_MASK		BIT_MASK(6)

#define CFG_RST_L_PCIE_PLL_MASK		BIT_MASK(7)

#define CFG_RST_L_NIC_S_PLL_MASK	BIT_MASK(8)

#define CFG_RST_L_HBM_N_PLL_MASK	BIT_MASK(9)

#define CFG_RST_L_TPC_N_PLL_MASK	BIT_MASK(10)

#define CFG_RST_L_MME_N_PLL_MASK	BIT_MASK(11)

#define CFG_RST_L_NIC_N_PLL_MASK	BIT_MASK(12)

#define CFG_RST_L_DMA_W_PLL_MASK	BIT_MASK(13)

#define CFG_RST_L_SIF_W_PLL_MASK	BIT_MASK(14)

#define CFG_RST_L_MESH_W_PLL_MASK	BIT_MASK(15)

#define CFG_RST_L_SRAM_W_PLL_MASK	BIT_MASK(16)

#define CFG_RST_L_DMA_E_PLL_MASK	BIT_MASK(17)

#define CFG_RST_L_SIF_E_PLL_MASK	BIT_MASK(18)

#define CFG_RST_L_MESH_E_PLL_MASK	BIT_MASK(19)

#define CFG_RST_L_SRAM_E_PLL_MASK	BIT_MASK(20)



#define CFG_RST_L_IF_1_MASK		BIT_MASK(21)

#define CFG_RST_L_IF_0_MASK		BIT_MASK(22)

#define CFG_RST_L_IF_2_MASK		BIT_MASK(23)

#define CFG_RST_L_IF_3_MASK		BIT_MASK(24)

#define CFG_RST_L_IF_MASK		GENMASK(24, 21)



#define CFG_RST_L_TPC_0_MASK		BIT_MASK(25)

#define CFG_RST_L_TPC_1_MASK		BIT_MASK(26)

#define CFG_RST_L_TPC_2_MASK		BIT_MASK(27)

#define CFG_RST_L_TPC_3_MASK		BIT_MASK(28)

#define CFG_RST_L_TPC_4_MASK		BIT_MASK(29)

#define CFG_RST_L_TPC_5_MASK		BIT_MASK(30)

#define CFG_RST_L_TPC_6_MASK		BIT_MASK(31)

#define CFG_RST_L_TPC_MASK		GENMASK(31, 25)



#define CFG_RST_H_TPC_7_MASK		BIT_MASK(0)



#define CFG_RST_H_MME_0_MASK		BIT_MASK(1)

#define CFG_RST_H_MME_1_MASK		BIT_MASK(2)

#define CFG_RST_H_MME_2_MASK		BIT_MASK(3)

#define CFG_RST_H_MME_3_MASK		BIT_MASK(4)

#define CFG_RST_H_MME_MASK		GENMASK(4, 1)



#define CFG_RST_H_HBM_0_MASK		BIT_MASK(5)

#define CFG_RST_H_HBM_1_MASK		BIT_MASK(6)

#define CFG_RST_H_HBM_2_MASK		BIT_MASK(7)

#define CFG_RST_H_HBM_3_MASK		BIT_MASK(8)

#define CFG_RST_H_HBM_MASK		GENMASK(8, 5)



#define CFG_RST_H_NIC_0_MASK		BIT_MASK(9)

#define CFG_RST_H_NIC_1_MASK		BIT_MASK(10)

#define CFG_RST_H_NIC_2_MASK		BIT_MASK(11)

#define CFG_RST_H_NIC_3_MASK		BIT_MASK(12)

#define CFG_RST_H_NIC_4_MASK		BIT_MASK(13)

#define CFG_RST_H_NIC_MASK		GENMASK(13, 9)



#define CFG_RST_H_SM_0_MASK		BIT_MASK(14)

#define CFG_RST_H_SM_1_MASK		BIT_MASK(15)

#define CFG_RST_H_SM_2_MASK		BIT_MASK(16)

#define CFG_RST_H_SM_3_MASK		BIT_MASK(17)

#define CFG_RST_H_SM_MASK		GENMASK(17, 14)



#define CFG_RST_H_DMA_0_MASK		BIT_MASK(18)

#define CFG_RST_H_DMA_1_MASK		BIT_MASK(19)

#define CFG_RST_H_DMA_MASK		GENMASK(19, 18)



#define CFG_RST_H_CPU_MASK		BIT_MASK(20)

#define CFG_RST_H_MMU_MASK		BIT_MASK(21)



#define UNIT_RST_L_PSOC_SHIFT		0

#define UNIT_RST_L_PCIE_SHIFT		1

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