Commit 655861e3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm 

Pull ARM fixes from Russell King.

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7406/1: hotplug: copy the affinity mask when forcefully migrating IRQs
  ARM: 7405/1: kexec: call platform_cpu_kill on the killer rather than the victim
  ARM: 7403/1: tls: remove covert channel via TPIDRURW
  ARM: 7401/1: mm: Fix section mismatches
  ARM: OMAP: fix DMA vs memory ordering
  ARM: 7390/1: dts: versatile-pb/ab fix MMC IRQs
  ARM: 7400/1: vfp: clear fpscr length and stride bits on entry to sig handler
  ARM: 7399/1: vfp: move user vfp state save/restore code out of signal.c
  ARM: 7398/1: l2x0: only write to debug registers on PL310
  ARM: 7397/1: l2x0: only apply workaround for erratum #753970 on PL310
  ARM: 7396/1: errata: only handle ARM erratum #326103 on affected cores
parents e7a7c9ab 5e7371de

arch/arm/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -1186,6 +1186,15 @@ if !MMU 
source "arch/arm/Kconfig-nommu"

endif



config ARM_ERRATA_326103

	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"

	depends on CPU_V6

	help

	  Executing a SWP instruction to read-only memory does not set bit 11

	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to

	  treat the access as a read, preventing a COW from occurring and

	  causing the faulting task to livelock.



config ARM_ERRATA_411920

	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"

	depends on CPU_V6 || CPU_V6K

arch/arm/boot/dts/versatile-ab.dts

+1 −1
Original line number Diff line number Diff line
@@ -173,7 +173,7 @@ 
			mmc@5000 {

				compatible = "arm,primecell";

				reg = < 0x5000 0x1000>;

				interrupts = <22>;

				interrupts = <22 34>;

			};

			kmi@6000 {

				compatible = "arm,pl050", "arm,primecell";

arch/arm/boot/dts/versatile-pb.dts

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 
			mmc@b000 {

				compatible = "arm,primecell";

				reg = <0xb000 0x1000>;

				interrupts = <23>;

				interrupts = <23 34>;

			};

		};

	};

arch/arm/include/asm/thread_info.h

+7 −0
Original line number Diff line number Diff line
@@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *); 
extern void vfp_sync_hwstate(struct thread_info *);

extern void vfp_flush_hwstate(struct thread_info *);



struct user_vfp;

struct user_vfp_exc;



extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,

					   struct user_vfp_exc __user *);

extern int vfp_restore_user_hwstate(struct user_vfp __user *,

				    struct user_vfp_exc __user *);

#endif



/*

arch/arm/include/asm/tls.h

+4 −0
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 


	.macro set_tls_v6k, tp, tmp1, tmp2

	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register

	mov	\tmp1, #0

	mcr	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register

	.endm



	.macro set_tls_v6, tp, tmp1, tmp2
@@ -15,6 +17,8 @@ 
	mov	\tmp2, #0xffff0fff

	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?

	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register

	movne	\tmp1, #0

	mcrne	p15, 0, \tmp1, c13, c0, 2	@ clear user r/w TLS register

	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0

	.endm

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