Commit 6545eae3 authored Aug 29, 2013 by Marc Zyngier Committed by Gleb Natapov Aug 30, 2013

ARM: KVM: vgic: fix GICD_ICFGRn access



All the code in handle_mmio_cfg_reg() assumes the offset has
been shifted right to accomodate for the 2:1 bit compression,
but this is only done when getting the register address.

Shift the offset early so the code works mostly unchanged.

Reported-by: Zhaobo (Bob, ERC) <zhaobo@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>

parent 986af8e0

virt/kvm/arm/vgic.c

+6 −2

Original line number	Diff line number	Diff line
		@@ -541,8 +541,12 @@ static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
		struct kvm_exit_mmio *mmio, phys_addr_t offset)
		{
		u32 val;
		u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
		vcpu->vcpu_id, offset >> 1);
		u32 *reg;

		offset >>= 1;
		reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
		vcpu->vcpu_id, offset);

		if (offset & 2)
		val = *reg >> 16;
		else

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