ASoC: cs47l92: Add codec driver for Cirrus Logic CS47L92 (6535e831) · Commits · 戴 / test

sound/soc/codecs/Kconfig

+6 −0

Original line number	Diff line number	Diff line
		@@ -75,6 +75,7 @@ config SND_SOC_ALL_CODECS
		select SND_SOC_CS47L35 if MFD_CS47L35
		select SND_SOC_CS47L85 if MFD_CS47L85
		select SND_SOC_CS47L90 if MFD_CS47L90
		select SND_SOC_CS47L92 if MFD_CS47L92
		select SND_SOC_CS53L30 if I2C
		select SND_SOC_CX20442 if TTY
		select SND_SOC_CX2072X if I2C
		@@ -597,6 +598,9 @@ config SND_SOC_CS47L85
		config SND_SOC_CS47L90
		tristate

		config SND_SOC_CS47L92
		tristate

		# Cirrus Logic Quad-Channel ADC
		config SND_SOC_CS53L30
		tristate "Cirrus Logic CS53L30 CODEC"
		@@ -730,10 +734,12 @@ config SND_SOC_MADERA
		default y if SND_SOC_CS47L35=y
		default y if SND_SOC_CS47L85=y
		default y if SND_SOC_CS47L90=y
		default y if SND_SOC_CS47L92=y
		default m if SND_SOC_CS47L15=m
		default m if SND_SOC_CS47L35=m
		default m if SND_SOC_CS47L85=m
		default m if SND_SOC_CS47L90=m
		default m if SND_SOC_CS47L92=m

		config SND_SOC_MAX98088
		tristate "Maxim MAX98088/9 Low-Power, Stereo Audio Codec"

sound/soc/codecs/Makefile

+2 −0

Original line number	Diff line number	Diff line
		@@ -69,6 +69,7 @@ snd-soc-cs47l24-objs := cs47l24.o
		snd-soc-cs47l35-objs := cs47l35.o
		snd-soc-cs47l85-objs := cs47l85.o
		snd-soc-cs47l90-objs := cs47l90.o
		snd-soc-cs47l92-objs := cs47l92.o
		snd-soc-cs53l30-objs := cs53l30.o
		snd-soc-cx20442-objs := cx20442.o
		snd-soc-cx2072x-objs := cx2072x.o
		@@ -351,6 +352,7 @@ obj-$(CONFIG_SND_SOC_CS47L15) += snd-soc-cs47l15.o
		obj-$(CONFIG_SND_SOC_CS47L35) += snd-soc-cs47l35.o
		obj-$(CONFIG_SND_SOC_CS47L85) += snd-soc-cs47l85.o
		obj-$(CONFIG_SND_SOC_CS47L90) += snd-soc-cs47l90.o
		obj-$(CONFIG_SND_SOC_CS47L92) += snd-soc-cs47l92.o
		obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o
		obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
		obj-$(CONFIG_SND_SOC_CX2072X) += snd-soc-cx2072x.o

sound/soc/codecs/cs47l92.c

0 → 100644

+2039 −0

File added.

Preview size limit exceeded, changes collapsed.

sound/soc/codecs/madera.c

+421 −9

Original line number	Diff line number	Diff line
		@@ -87,6 +87,16 @@
		#define MADERA_FLLAO_MIN_N 4
		#define MADERA_FLLAO_MAX_N 1023
		#define MADERA_FLLAO_MAX_FBDIV 254
		#define MADERA_FLLHJ_INT_MAX_N 1023
		#define MADERA_FLLHJ_INT_MIN_N 1
		#define MADERA_FLLHJ_FRAC_MAX_N 255
		#define MADERA_FLLHJ_FRAC_MIN_N 4
		#define MADERA_FLLHJ_LOW_THRESH 192000
		#define MADERA_FLLHJ_MID_THRESH 1152000
		#define MADERA_FLLHJ_MAX_THRESH 13000000
		#define MADERA_FLLHJ_LOW_GAINS 0x23f0
		#define MADERA_FLLHJ_MID_GAINS 0x22f2
		#define MADERA_FLLHJ_HIGH_GAINS 0x21f0

		#define MADERA_FLL_SYNCHRONISER_OFFS 0x10
		#define CS47L35_FLL_SYNCHRONISER_OFFS 0xE
		@@ -96,6 +106,7 @@
		#define MADERA_FLL_CONTROL_4_OFFS 0x4
		#define MADERA_FLL_CONTROL_5_OFFS 0x5
		#define MADERA_FLL_CONTROL_6_OFFS 0x6
		#define MADERA_FLL_GAIN_OFFS 0x8
		#define MADERA_FLL_CONTROL_7_OFFS 0x9
		#define MADERA_FLL_EFS_2_OFFS 0xA
		#define MADERA_FLL_SYNCHRONISER_1_OFFS 0x1
		@@ -107,6 +118,9 @@
		#define MADERA_FLL_SYNCHRONISER_7_OFFS 0x7
		#define MADERA_FLL_SPREAD_SPECTRUM_OFFS 0x9
		#define MADERA_FLL_GPIO_CLOCK_OFFS 0xA
		#define MADERA_FLL_CONTROL_10_OFFS 0xA
		#define MADERA_FLL_CONTROL_11_OFFS 0xB
		#define MADERA_FLL1_DIGITAL_TEST_1_OFFS 0xD

		#define MADERA_FLLAO_CONTROL_1_OFFS 0x1
		#define MADERA_FLLAO_CONTROL_2_OFFS 0x2
		@@ -1871,6 +1885,18 @@ const struct soc_enum madera_asrc1_rate[] = {
		};
		EXPORT_SYMBOL_GPL(madera_asrc1_rate);

		const struct soc_enum madera_asrc1_bidir_rate[] = {
		SOC_VALUE_ENUM_SINGLE(MADERA_ASRC1_RATE1,
		MADERA_ASRC1_RATE1_SHIFT, 0xf,
		MADERA_RATE_ENUM_SIZE,
		madera_rate_text, madera_rate_val),
		SOC_VALUE_ENUM_SINGLE(MADERA_ASRC1_RATE2,
		MADERA_ASRC1_RATE2_SHIFT, 0xf,
		MADERA_RATE_ENUM_SIZE,
		madera_rate_text, madera_rate_val),
		};
		EXPORT_SYMBOL_GPL(madera_asrc1_bidir_rate);

		const struct soc_enum madera_asrc2_rate[] = {
		SOC_VALUE_ENUM_SINGLE(MADERA_ASRC2_RATE1,
		MADERA_ASRC2_RATE1_SHIFT, 0xf,
		@@ -2250,6 +2276,9 @@ int madera_out_ev(struct snd_soc_dapm_widget *w,
		switch (madera->type) {
		case CS47L90:
		case CS47L91:
		case CS42L92:
		case CS47L92:
		case CS47L93:
		out_up_delay = 6;
		break;
		default:
		@@ -2365,9 +2394,17 @@ int madera_hp_ev(struct snd_soc_dapm_widget *w,
		madera->hp_ena &= ~mask;
		madera->hp_ena \|= val;

		switch (madera->type) {
		case CS42L92:
		case CS47L92:
		case CS47L93:
		break;
		default:
		/* if OUT1 is routed to EPOUT, ignore HP clamp and impedance */
		regmap_read(madera->regmap, MADERA_OUTPUT_ENABLES_1, &ep_sel);
		ep_sel &= MADERA_EP_SEL_MASK;
		break;
		}

		/* Force off if HPDET has disabled the clamp for this output */
		if (!ep_sel &&
		@@ -2543,6 +2580,58 @@ static int madera_get_dspclk_setting(struct madera *madera,
		}
		}

		static int madera_set_outclk(struct snd_soc_component *component,
		unsigned int source, unsigned int freq)
		{
		int div, div_inc, rate;

		switch (source) {
		case MADERA_OUTCLK_SYSCLK:
		dev_dbg(component->dev, "Configured OUTCLK to SYSCLK\n");
		snd_soc_component_update_bits(component, MADERA_OUTPUT_RATE_1,
		MADERA_OUT_CLK_SRC_MASK, source);
		return 0;
		case MADERA_OUTCLK_ASYNCCLK:
		dev_dbg(component->dev, "Configured OUTCLK to ASYNCCLK\n");
		snd_soc_component_update_bits(component, MADERA_OUTPUT_RATE_1,
		MADERA_OUT_CLK_SRC_MASK, source);
		return 0;
		case MADERA_OUTCLK_MCLK1:
		case MADERA_OUTCLK_MCLK2:
		case MADERA_OUTCLK_MCLK3:
		break;
		default:
		return -EINVAL;
		}

		if (freq % 4000)
		rate = 5644800;
		else
		rate = 6144000;

		div = 1;
		div_inc = 0;
		while (div <= 8) {
		if (freq / div == rate && !(freq % div)) {
		dev_dbg(component->dev, "Configured %dHz OUTCLK\n", rate);
		snd_soc_component_update_bits(component,
		MADERA_OUTPUT_RATE_1,
		MADERA_OUT_EXT_CLK_DIV_MASK \|
		MADERA_OUT_CLK_SRC_MASK,
		(div_inc << MADERA_OUT_EXT_CLK_DIV_SHIFT) \|
		source);
		return 0;
		}
		div_inc++;
		div *= 2;
		}

		dev_err(component->dev,
		"Unable to generate %dHz OUTCLK from %dHz MCLK\n",
		rate, freq);
		return -EINVAL;
		}

		int madera_set_sysclk(struct snd_soc_component *component, int clk_id,
		int source, unsigned int freq, int dir)
		{
		@@ -2579,6 +2668,8 @@ int madera_set_sysclk(struct snd_soc_component *component, int clk_id,
		case MADERA_CLK_OPCLK:
		case MADERA_CLK_ASYNC_OPCLK:
		return madera_set_opclk(component, clk_id, freq);
		case MADERA_CLK_OUTCLK:
		return madera_set_outclk(component, source, freq);
		default:
		return -EINVAL;
		}
		@@ -2792,6 +2883,10 @@ static const unsigned int madera_sr_vals[] = {
		#define MADERA_192K_44K1_RATE_MASK 0x003E00
		#define MADERA_192K_RATE_MASK (MADERA_192K_48K_RATE_MASK \| \
		MADERA_192K_44K1_RATE_MASK)
		#define MADERA_384K_48K_RATE_MASK 0x0F007E
		#define MADERA_384K_44K1_RATE_MASK 0x007E00
		#define MADERA_384K_RATE_MASK (MADERA_384K_48K_RATE_MASK \| \
		MADERA_384K_44K1_RATE_MASK)

		static const struct snd_pcm_hw_constraint_list madera_constraint = {
		.count = ARRAY_SIZE(madera_sr_vals),
		@@ -2804,6 +2899,7 @@ static int madera_startup(struct snd_pcm_substream *substream,
		struct snd_soc_component *component = dai->component;
		struct madera_priv *priv = snd_soc_component_get_drvdata(component);
		struct madera_dai_priv *dai_priv = &priv->dai[dai->id - 1];
		struct madera *madera = priv->madera;
		unsigned int base_rate;

		if (!substream->runtime)
		@@ -2823,12 +2919,26 @@ static int madera_startup(struct snd_pcm_substream *substream,
		return 0;
		}

		switch (madera->type) {
		case CS42L92:
		case CS47L92:
		case CS47L93:
		if (base_rate == 0)
		dai_priv->constraint.mask = MADERA_384K_RATE_MASK;
		else if (base_rate % 4000)
		dai_priv->constraint.mask = MADERA_384K_44K1_RATE_MASK;
		else
		dai_priv->constraint.mask = MADERA_384K_48K_RATE_MASK;
		break;
		default:
		if (base_rate == 0)
		dai_priv->constraint.mask = MADERA_192K_RATE_MASK;
		else if (base_rate % 4000)
		dai_priv->constraint.mask = MADERA_192K_44K1_RATE_MASK;
		else
		dai_priv->constraint.mask = MADERA_192K_48K_RATE_MASK;
		break;
		}

		return snd_pcm_hw_constraint_list(substream->runtime, 0,
		SNDRV_PCM_HW_PARAM_RATE,
		@@ -4149,6 +4259,308 @@ int madera_set_fll_ao_refclk(struct madera_fll *fll, int source,
		}
		EXPORT_SYMBOL_GPL(madera_set_fll_ao_refclk);

		static int madera_fllhj_disable(struct madera_fll *fll)
		{
		struct madera *madera = fll->madera;
		bool change;

		madera_fll_dbg(fll, "Disabling FLL\n");

		/* Disable lockdet, but don't set ctrl_upd update but. This allows the
		* lock status bit to clear as normal, but should the FLL be enabled
		* again due to a control clock being required, the lock won't re-assert
		* as the FLL config registers are automatically applied when the FLL
		* enables.
		*/
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_11_OFFS,
		MADERA_FLL1_LOCKDET_MASK, 0);
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_1_OFFS,
		MADERA_FLL1_HOLD_MASK, MADERA_FLL1_HOLD_MASK);
		regmap_update_bits_check(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_1_OFFS,
		MADERA_FLL1_ENA_MASK, 0, &change);

		madera_wait_for_fll(fll, false);

		/* ctrl_up gates the writes to all the fll's registers, setting it to 0
		* here ensures that after a runtime suspend/resume cycle when one
		* enables the fll then ctrl_up is the last bit that is configured
		* by the fll enable code rather than the cache sync operation which
		* would have updated it much earlier before writing out all fll
		* registers
		*/
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_2_OFFS,
		MADERA_FLL1_CTRL_UPD_MASK, 0);

		if (change)
		pm_runtime_put_autosuspend(madera->dev);

		return 0;
		}

		static int madera_fllhj_apply(struct madera_fll *fll, int fin)
		{
		struct madera *madera = fll->madera;
		int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd;
		bool frac = false;
		unsigned int fll_n, min_n, max_n, ratio, theta, lambda;
		unsigned int gains, val, num;

		madera_fll_dbg(fll, "fin=%d, fout=%d\n", fin, fll->fout);

		for (refdiv = 0; refdiv < 4; refdiv++)
		if ((fin / (1 << refdiv)) <= MADERA_FLLHJ_MAX_THRESH)
		break;

		fref = fin / (1 << refdiv);

		/* Use simple heuristic approach to find a configuration that
		* should work for most input clocks.
		*/
		fast_clk = 0;
		fout = fll->fout;
		frac = fout % fref;

		if (fref < MADERA_FLLHJ_LOW_THRESH) {
		lockdet_thr = 2;
		gains = MADERA_FLLHJ_LOW_GAINS;
		if (frac)
		fbdiv = 256;
		else
		fbdiv = 4;
		} else if (fref < MADERA_FLLHJ_MID_THRESH) {
		lockdet_thr = 8;
		gains = MADERA_FLLHJ_MID_GAINS;
		fbdiv = 1;
		} else {
		lockdet_thr = 8;
		gains = MADERA_FLLHJ_HIGH_GAINS;
		fbdiv = 1;
		/* For high speed input clocks, enable 300MHz fast oscillator
		* when we're in fractional divider mode.
		*/
		if (frac) {
		fast_clk = 0x3;
		fout = fll->fout * 6;
		}
		}
		/* Use high performance mode for fractional configurations. */
		if (frac) {
		hp = 0x3;
		min_n = MADERA_FLLHJ_FRAC_MIN_N;
		max_n = MADERA_FLLHJ_FRAC_MAX_N;
		} else {
		hp = 0x0;
		min_n = MADERA_FLLHJ_INT_MIN_N;
		max_n = MADERA_FLLHJ_INT_MAX_N;
		}

		ratio = fout / fref;

		madera_fll_dbg(fll, "refdiv=%d, fref=%d, frac:%d\n",
		refdiv, fref, frac);

		while (ratio / fbdiv < min_n) {
		fbdiv /= 2;
		if (fbdiv < 1) {
		madera_fll_err(fll, "FBDIV (%d) must be >= 1\n", fbdiv);
		return -EINVAL;
		}
		}
		while (frac && (ratio / fbdiv > max_n)) {
		fbdiv *= 2;
		if (fbdiv >= 1024) {
		madera_fll_err(fll, "FBDIV (%u) >= 1024\n", fbdiv);
		return -EINVAL;
		}
		}

		madera_fll_dbg(fll, "lockdet=%d, hp=0x%x, fbdiv:%d\n",
		lockdet_thr, hp, fbdiv);

		/* Calculate N.K values */
		fllgcd = gcd(fout, fbdiv * fref);
		num = fout / fllgcd;
		lambda = (fref * fbdiv) / fllgcd;
		fll_n = num / lambda;
		theta = num % lambda;

		madera_fll_dbg(fll, "fll_n=%d, gcd=%d, theta=%d, lambda=%d\n",
		fll_n, fllgcd, theta, lambda);

		/* Some sanity checks before any registers are written. */
		if (fll_n < min_n \|\| fll_n > max_n) {
		madera_fll_err(fll, "N not in valid %s mode range %d-%d: %d\n",
		frac ? "fractional" : "integer", min_n, max_n,
		fll_n);
		return -EINVAL;
		}
		if (fbdiv < 1 \|\| (frac && fbdiv >= 1024) \|\| (!frac && fbdiv >= 256)) {
		madera_fll_err(fll, "Invalid fbdiv for %s mode (%u)\n",
		frac ? "fractional" : "integer", fbdiv);
		return -EINVAL;
		}

		/* clear the ctrl_upd bit to guarantee we write to it later. */
		regmap_write(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_2_OFFS,
		fll_n << MADERA_FLL1_N_SHIFT);
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_3_OFFS,
		MADERA_FLL1_THETA_MASK,
		theta << MADERA_FLL1_THETA_SHIFT);
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_4_OFFS,
		MADERA_FLL1_LAMBDA_MASK,
		lambda << MADERA_FLL1_LAMBDA_SHIFT);
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_5_OFFS,
		MADERA_FLL1_FB_DIV_MASK,
		fbdiv << MADERA_FLL1_FB_DIV_SHIFT);
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_6_OFFS,
		MADERA_FLL1_REFCLK_DIV_MASK,
		refdiv << MADERA_FLL1_REFCLK_DIV_SHIFT);
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_GAIN_OFFS,
		0xffff,
		gains);
		val = hp << MADERA_FLL1_HP_SHIFT;
		val \|= 1 << MADERA_FLL1_PHASEDET_ENA_SHIFT;
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_10_OFFS,
		MADERA_FLL1_HP_MASK \| MADERA_FLL1_PHASEDET_ENA_MASK,
		val);
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_11_OFFS,
		MADERA_FLL1_LOCKDET_THR_MASK,
		lockdet_thr << MADERA_FLL1_LOCKDET_THR_SHIFT);
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL1_DIGITAL_TEST_1_OFFS,
		MADERA_FLL1_SYNC_EFS_ENA_MASK \|
		MADERA_FLL1_CLK_VCO_FAST_SRC_MASK,
		fast_clk);

		return 0;
		}

		static int madera_fllhj_enable(struct madera_fll *fll)
		{
		struct madera *madera = fll->madera;
		int already_enabled = madera_is_enabled_fll(fll, fll->base);
		int ret;

		if (already_enabled < 0)
		return already_enabled;

		if (!already_enabled)
		pm_runtime_get_sync(madera->dev);

		madera_fll_dbg(fll, "Enabling FLL, initially %s\n",
		already_enabled ? "enabled" : "disabled");

		/* FLLn_HOLD must be set before configuring any registers */
		regmap_update_bits(fll->madera->regmap,
		fll->base + MADERA_FLL_CONTROL_1_OFFS,
		MADERA_FLL1_HOLD_MASK,
		MADERA_FLL1_HOLD_MASK);

		/* Apply refclk */
		ret = madera_fllhj_apply(fll, fll->ref_freq);
		if (ret) {
		madera_fll_err(fll, "Failed to set FLL: %d\n", ret);
		goto out;
		}
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_1_OFFS,
		CS47L92_FLL1_REFCLK_SRC_MASK,
		fll->ref_src << CS47L92_FLL1_REFCLK_SRC_SHIFT);

		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_1_OFFS,
		MADERA_FLL1_ENA_MASK,
		MADERA_FLL1_ENA_MASK);

		out:
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_11_OFFS,
		MADERA_FLL1_LOCKDET_MASK,
		MADERA_FLL1_LOCKDET_MASK);

		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_2_OFFS,
		MADERA_FLL1_CTRL_UPD_MASK,
		MADERA_FLL1_CTRL_UPD_MASK);

		/* Release the hold so that flln locks to external frequency */
		regmap_update_bits(madera->regmap,
		fll->base + MADERA_FLL_CONTROL_1_OFFS,
		MADERA_FLL1_HOLD_MASK,
		0);

		if (!already_enabled)
		madera_wait_for_fll(fll, true);

		return 0;
		}

		static int madera_fllhj_validate(struct madera_fll *fll,
		unsigned int ref_in,
		unsigned int fout)
		{
		if (fout && !ref_in) {
		madera_fll_err(fll, "fllout set without valid input clk\n");
		return -EINVAL;
		}

		if (fll->fout && fout != fll->fout) {
		madera_fll_err(fll, "Can't change output on active FLL\n");
		return -EINVAL;
		}

		if (ref_in / MADERA_FLL_MAX_REFDIV > MADERA_FLLHJ_MAX_THRESH) {
		madera_fll_err(fll, "Can't scale %dMHz to <=13MHz\n", ref_in);
		return -EINVAL;
		}

		return 0;
		}

		int madera_fllhj_set_refclk(struct madera_fll *fll, int source,
		unsigned int fin, unsigned int fout)
		{
		int ret = 0;

		/* To remain consistent with previous FLLs, we expect fout to be
		* provided in the form of the required sysclk rate, which is
		* 2x the calculated fll out.
		*/
		if (fout)
		fout /= 2;

		if (fll->ref_src == source && fll->ref_freq == fin &&
		fll->fout == fout)
		return 0;

		if (fin && fout && madera_fllhj_validate(fll, fin, fout))
		return -EINVAL;

		fll->ref_src = source;
		fll->ref_freq = fin;
		fll->fout = fout;

		if (fout)
		ret = madera_fllhj_enable(fll);
		else
		madera_fllhj_disable(fll);

		return ret;
		}
		EXPORT_SYMBOL_GPL(madera_fllhj_set_refclk);

		/**
		* madera_set_output_mode - Set the mode of the specified output
		*

sound/soc/codecs/madera.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -47,6 +47,7 @@
		#define MADERA_CLK_SYSCLK_3 6
		#define MADERA_CLK_ASYNCCLK_2 7
		#define MADERA_CLK_DSPCLK 8
		#define MADERA_CLK_OUTCLK 9

		#define MADERA_CLK_SRC_MCLK1 0x0
		#define MADERA_CLK_SRC_MCLK2 0x1
		@@ -61,6 +62,12 @@
		#define MADERA_CLK_SRC_AIF4BCLK 0xB
		#define MADERA_CLK_SRC_FLLAO 0xF

		#define MADERA_OUTCLK_SYSCLK 0
		#define MADERA_OUTCLK_ASYNCCLK 1
		#define MADERA_OUTCLK_MCLK1 4
		#define MADERA_OUTCLK_MCLK2 5
		#define MADERA_OUTCLK_MCLK3 6

		#define MADERA_MIXER_VOL_MASK 0x00FE
		#define MADERA_MIXER_VOL_SHIFT 1
		#define MADERA_MIXER_VOL_WIDTH 7
		@@ -326,6 +333,7 @@ extern const struct soc_enum madera_sample_rate[];
		extern const struct soc_enum madera_isrc_fsl[];
		extern const struct soc_enum madera_isrc_fsh[];
		extern const struct soc_enum madera_asrc1_rate[];
		extern const struct soc_enum madera_asrc1_bidir_rate[];
		extern const struct soc_enum madera_asrc2_rate[];
		extern const struct soc_enum madera_dfc_width[];
		extern const struct soc_enum madera_dfc_type[];
		@@ -403,6 +411,8 @@ int madera_set_fll_syncclk(struct madera_fll *fll, int source,
		unsigned int fref, unsigned int fout);
		int madera_set_fll_ao_refclk(struct madera_fll *fll, int source,
		unsigned int fin, unsigned int fout);
		int madera_fllhj_set_refclk(struct madera_fll *fll, int source,
		unsigned int fin, unsigned int fout);

		int madera_core_init(struct madera_priv *priv);
		int madera_core_free(struct madera_priv *priv);

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