Commit 65344ba9 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'amd-xgbe-updates' 



Tom Lendacky says:

====================
amd-xgbe: AMD XGBE driver updates 2016-06-28

The following updates and fixes are included in this driver update series:

- Simplify mailbox interface code
- Fix SFP supported and advertising settings
- Fix PTP initialization register usage
- Insure there is timestamp skb present before using it
- Add a timeout to timestamp register updates
- Handle return code from software reset function
- Some fixes for handling 2.5Gbps rates
- Limit I2C error messages
- Fix non-DMA interrupt handling through tasklet usage
- Add NUMA affinity support for memory allocations
- Add NUMA affinity support for interrupts
- Prepare for more fine-grained cache coherency controls
- Simplify setting the DMA burst length programming
- Performance improvements

This patch series is based on net-next.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e3ef6983 6f595959

drivers/net/ethernet/amd/xgbe/xgbe-common.h

+23 −30
Original line number Diff line number Diff line
@@ -123,38 +123,13 @@ 
#define DMA_ISR				0x3008

#define DMA_AXIARCR			0x3010

#define DMA_AXIAWCR			0x3018

#define DMA_AXIAWARCR			0x301c

#define DMA_DSR0			0x3020

#define DMA_DSR1			0x3024

#define DMA_TXEDMACR			0x3040

#define DMA_RXEDMACR			0x3044



/* DMA register entry bit positions and sizes */

#define DMA_AXIARCR_DRC_INDEX		0

#define DMA_AXIARCR_DRC_WIDTH		4

#define DMA_AXIARCR_DRD_INDEX		4

#define DMA_AXIARCR_DRD_WIDTH		2

#define DMA_AXIARCR_TEC_INDEX		8

#define DMA_AXIARCR_TEC_WIDTH		4

#define DMA_AXIARCR_TED_INDEX		12

#define DMA_AXIARCR_TED_WIDTH		2

#define DMA_AXIARCR_THC_INDEX		16

#define DMA_AXIARCR_THC_WIDTH		4

#define DMA_AXIARCR_THD_INDEX		20

#define DMA_AXIARCR_THD_WIDTH		2

#define DMA_AXIAWCR_DWC_INDEX		0

#define DMA_AXIAWCR_DWC_WIDTH		4

#define DMA_AXIAWCR_DWD_INDEX		4

#define DMA_AXIAWCR_DWD_WIDTH		2

#define DMA_AXIAWCR_RPC_INDEX		8

#define DMA_AXIAWCR_RPC_WIDTH		4

#define DMA_AXIAWCR_RPD_INDEX		12

#define DMA_AXIAWCR_RPD_WIDTH		2

#define DMA_AXIAWCR_RHC_INDEX		16

#define DMA_AXIAWCR_RHC_WIDTH		4

#define DMA_AXIAWCR_RHD_INDEX		20

#define DMA_AXIAWCR_RHD_WIDTH		2

#define DMA_AXIAWCR_TDC_INDEX		24

#define DMA_AXIAWCR_TDC_WIDTH		4

#define DMA_AXIAWCR_TDD_INDEX		28

#define DMA_AXIAWCR_TDD_WIDTH		2

#define DMA_ISR_MACIS_INDEX		17

#define DMA_ISR_MACIS_WIDTH		1

#define DMA_ISR_MTLIS_INDEX		16
@@ -163,14 +138,31 @@ 
#define DMA_MR_INTM_WIDTH		2

#define DMA_MR_SWR_INDEX		0

#define DMA_MR_SWR_WIDTH		1

#define DMA_RXEDMACR_RDPS_INDEX		0

#define DMA_RXEDMACR_RDPS_WIDTH		3

#define DMA_SBMR_AAL_INDEX		12

#define DMA_SBMR_AAL_WIDTH		1

#define DMA_SBMR_EAME_INDEX		11

#define DMA_SBMR_EAME_WIDTH		1

#define DMA_SBMR_BLEN_256_INDEX		7

#define DMA_SBMR_BLEN_256_WIDTH		1

#define DMA_SBMR_BLEN_INDEX		1

#define DMA_SBMR_BLEN_WIDTH		7

#define DMA_SBMR_RD_OSR_LMT_INDEX	16

#define DMA_SBMR_RD_OSR_LMT_WIDTH	6

#define DMA_SBMR_UNDEF_INDEX		0

#define DMA_SBMR_UNDEF_WIDTH		1

#define DMA_SBMR_WR_OSR_LMT_INDEX	24

#define DMA_SBMR_WR_OSR_LMT_WIDTH	6

#define DMA_TXEDMACR_TDPS_INDEX		0

#define DMA_TXEDMACR_TDPS_WIDTH		3



/* DMA register values */

#define DMA_SBMR_BLEN_256		256

#define DMA_SBMR_BLEN_128		128

#define DMA_SBMR_BLEN_64		64

#define DMA_SBMR_BLEN_32		32

#define DMA_SBMR_BLEN_16		16

#define DMA_SBMR_BLEN_8			8

#define DMA_SBMR_BLEN_4			4

#define DMA_DSR_RPS_WIDTH		4

#define DMA_DSR_TPS_WIDTH		4

#define DMA_DSR_Q_WIDTH			(DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
@@ -959,6 +951,7 @@ 
#define XP_DRIVER_INT_RO		0x0064

#define XP_DRIVER_SCRATCH_0		0x0068

#define XP_DRIVER_SCRATCH_1		0x006c

#define XP_INT_REISSUE_EN		0x0074

#define XP_INT_EN			0x0078

#define XP_I2C_MUTEX			0x0080

#define XP_MDIO_MUTEX			0x0084

drivers/net/ethernet/amd/xgbe/xgbe-desc.c

+64 −30
Original line number Diff line number Diff line
@@ -176,8 +176,8 @@ static void xgbe_free_ring_resources(struct xgbe_prv_data *pdata) 


	DBGPR("-->xgbe_free_ring_resources\n");



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

	for (i = 0; i < pdata->channel_count; i++) {

		channel = pdata->channel[i];

		xgbe_free_ring(pdata, channel->tx_ring);

		xgbe_free_ring(pdata, channel->rx_ring);

	}
@@ -185,34 +185,60 @@ static void xgbe_free_ring_resources(struct xgbe_prv_data *pdata) 
	DBGPR("<--xgbe_free_ring_resources\n");

}



static void *xgbe_alloc_node(size_t size, int node)

{

	void *mem;



	mem = kzalloc_node(size, GFP_KERNEL, node);

	if (!mem)

		mem = kzalloc(size, GFP_KERNEL);



	return mem;

}



static void *xgbe_dma_alloc_node(struct device *dev, size_t size,

				 dma_addr_t *dma, int node)

{

	void *mem;

	int cur_node = dev_to_node(dev);



	set_dev_node(dev, node);

	mem = dma_alloc_coherent(dev, size, dma, GFP_KERNEL);

	set_dev_node(dev, cur_node);



	if (!mem)

		mem = dma_alloc_coherent(dev, size, dma, GFP_KERNEL);



	return mem;

}



static int xgbe_init_ring(struct xgbe_prv_data *pdata,

			  struct xgbe_ring *ring, unsigned int rdesc_count)

{

	DBGPR("-->xgbe_init_ring\n");

	size_t size;



	if (!ring)

		return 0;



	/* Descriptors */

	size = rdesc_count * sizeof(struct xgbe_ring_desc);



	ring->rdesc_count = rdesc_count;

	ring->rdesc = dma_alloc_coherent(pdata->dev,

					 (sizeof(struct xgbe_ring_desc) *

					  rdesc_count), &ring->rdesc_dma,

					 GFP_KERNEL);

	ring->rdesc = xgbe_dma_alloc_node(pdata->dev, size, &ring->rdesc_dma,

					  ring->node);

	if (!ring->rdesc)

		return -ENOMEM;



	/* Descriptor information */

	ring->rdata = kcalloc(rdesc_count, sizeof(struct xgbe_ring_data),

			      GFP_KERNEL);

	size = rdesc_count * sizeof(struct xgbe_ring_data);



	ring->rdata = xgbe_alloc_node(size, ring->node);

	if (!ring->rdata)

		return -ENOMEM;



	netif_dbg(pdata, drv, pdata->netdev,

		  "rdesc=%p, rdesc_dma=%pad, rdata=%p\n",

		  ring->rdesc, &ring->rdesc_dma, ring->rdata);



	DBGPR("<--xgbe_init_ring\n");

		  "rdesc=%p, rdesc_dma=%pad, rdata=%p, node=%d\n",

		  ring->rdesc, &ring->rdesc_dma, ring->rdata, ring->node);



	return 0;

}
@@ -223,10 +249,8 @@ static int xgbe_alloc_ring_resources(struct xgbe_prv_data *pdata) 
	unsigned int i;

	int ret;



	DBGPR("-->xgbe_alloc_ring_resources\n");



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

	for (i = 0; i < pdata->channel_count; i++) {

		channel = pdata->channel[i];

		netif_dbg(pdata, drv, pdata->netdev, "%s - Tx ring:\n",

			  channel->name);
@@ -250,8 +274,6 @@ static int xgbe_alloc_ring_resources(struct xgbe_prv_data *pdata) 
		}

	}



	DBGPR("<--xgbe_alloc_ring_resources\n");



	return 0;



err_ring:
@@ -261,21 +283,33 @@ err_ring: 
}



static int xgbe_alloc_pages(struct xgbe_prv_data *pdata,

			    struct xgbe_page_alloc *pa, gfp_t gfp, int order)

			    struct xgbe_page_alloc *pa, int alloc_order,

			    int node)

{

	struct page *pages = NULL;

	dma_addr_t pages_dma;

	int ret;

	gfp_t gfp;

	int order, ret;



again:

	order = alloc_order;



	/* Try to obtain pages, decreasing order if necessary */

	gfp |= __GFP_COLD | __GFP_COMP | __GFP_NOWARN;

	gfp = GFP_ATOMIC | __GFP_COLD | __GFP_COMP | __GFP_NOWARN;

	while (order >= 0) {

		pages = alloc_pages(gfp, order);

		pages = alloc_pages_node(node, gfp, order);

		if (pages)

			break;



		order--;

	}



	/* If we couldn't get local pages, try getting from anywhere */

	if (!pages && (node != NUMA_NO_NODE)) {

		node = NUMA_NO_NODE;

		goto again;

	}



	if (!pages)

		return -ENOMEM;
@@ -327,14 +361,14 @@ static int xgbe_map_rx_buffer(struct xgbe_prv_data *pdata, 
	int ret;



	if (!ring->rx_hdr_pa.pages) {

		ret = xgbe_alloc_pages(pdata, &ring->rx_hdr_pa, GFP_ATOMIC, 0);

		ret = xgbe_alloc_pages(pdata, &ring->rx_hdr_pa, 0, ring->node);

		if (ret)

			return ret;

	}



	if (!ring->rx_buf_pa.pages) {

		ret = xgbe_alloc_pages(pdata, &ring->rx_buf_pa, GFP_ATOMIC,

				       PAGE_ALLOC_COSTLY_ORDER);

		ret = xgbe_alloc_pages(pdata, &ring->rx_buf_pa,

				       PAGE_ALLOC_COSTLY_ORDER, ring->node);

		if (ret)

			return ret;

	}
@@ -362,8 +396,8 @@ static void xgbe_wrapper_tx_descriptor_init(struct xgbe_prv_data *pdata) 


	DBGPR("-->xgbe_wrapper_tx_descriptor_init\n");



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

	for (i = 0; i < pdata->channel_count; i++) {

		channel = pdata->channel[i];

		ring = channel->tx_ring;

		if (!ring)

			break;
@@ -403,8 +437,8 @@ static void xgbe_wrapper_rx_descriptor_init(struct xgbe_prv_data *pdata) 


	DBGPR("-->xgbe_wrapper_rx_descriptor_init\n");



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

	for (i = 0; i < pdata->channel_count; i++) {

		channel = pdata->channel[i];

		ring = channel->rx_ring;

		if (!ring)

			break;

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

+97 −147
Original line number Diff line number Diff line
@@ -174,58 +174,30 @@ static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 
	return ret;

}



static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)

static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int pblx8, pbl;

	unsigned int i;



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++)

		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,

				       pdata->pblx8);

	pblx8 = DMA_PBL_X8_DISABLE;

	pbl = pdata->pbl;



	return 0;

	if (pdata->pbl > 32) {

		pblx8 = DMA_PBL_X8_ENABLE;

		pbl >>= 3;

	}



static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)

{

	return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);

}

	for (i = 0; i < pdata->channel_count; i++) {

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,

				       pblx8);



static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;

		if (pdata->channel[i]->tx_ring)

			XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,

					       PBL, pbl);



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->tx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,

				       pdata->tx_pbl);

	}



	return 0;

}



static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)

{

	return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);

}



static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->rx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,

				       pdata->rx_pbl);

		if (pdata->channel[i]->rx_ring)

			XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,

					       PBL, pbl);

	}



	return 0;
@@ -233,15 +205,13 @@ static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata) 


static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->tx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->tx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,

				       pdata->tx_osp_mode);

	}
@@ -292,15 +262,13 @@ static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 


static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->rx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->rx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT,

				       pdata->rx_riwt);

	}
@@ -314,44 +282,38 @@ static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 


static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->rx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->rx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ,

				       pdata->rx_buf_size);

	}

}



static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->tx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->tx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1);

	}

}



static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->rx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->rx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1);

	}



	XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
@@ -651,8 +613,9 @@ static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 
		XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM,

				   pdata->channel_irq_mode);



	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

	for (i = 0; i < pdata->channel_count; i++) {

		channel = pdata->channel[i];



		/* Clear all the interrupts which are set */

		dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);

		XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
@@ -1497,26 +1460,37 @@ static void xgbe_rx_desc_init(struct xgbe_channel *channel) 
static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,

				      unsigned int addend)

{

	unsigned int count = 10000;



	/* Set the addend register value and tell the device */

	XGMAC_IOWRITE(pdata, MAC_TSAR, addend);

	XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);



	/* Wait for addend update to complete */

	while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))

	while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))

		udelay(5);



	if (!count)

		netdev_err(pdata->netdev,

			   "timed out updating timestamp addend register\n");

}



static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,

				 unsigned int nsec)

{

	unsigned int count = 10000;



	/* Set the time values and tell the device */

	XGMAC_IOWRITE(pdata, MAC_STSUR, sec);

	XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);

	XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);



	/* Wait for time update to complete */

	while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))

	while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))

		udelay(5);



	if (!count)

		netdev_err(pdata->netdev, "timed out initializing timestamp\n");

}



static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
@@ -2140,37 +2114,38 @@ static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 


static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)

{

	unsigned int sbmr;



	sbmr = XGMAC_IOREAD(pdata, DMA_SBMR);



	/* Set enhanced addressing mode */

	XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);

	XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1);



	/* Set the System Bus mode */

	XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);

	XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);

	XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1);

	XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);

	XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);

	XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);

	XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);



	XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr);



	/* Set descriptor fetching threshold */

	if (pdata->vdata->tx_desc_prefetch)

		XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS,

				   pdata->vdata->tx_desc_prefetch);



	if (pdata->vdata->rx_desc_prefetch)

		XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS,

				   pdata->vdata->rx_desc_prefetch);

}



static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)

{

	unsigned int arcache, awcache;



	arcache = 0;

	XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);

	XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);

	XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);

	XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);

	XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);

	XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);

	XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);



	awcache = 0;

	XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);

	XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);

	XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);

	XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);

	XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);

	XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);

	XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);

	XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);

	XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);

	XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);

	XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);

	if (pdata->awarcr)

		XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr);

}



static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
@@ -3202,16 +3177,14 @@ static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, 


static void xgbe_enable_tx(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	/* Enable each Tx DMA channel */

	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->tx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->tx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);

	}



	/* Enable each Tx queue */
@@ -3225,7 +3198,6 @@ static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 


static void xgbe_disable_tx(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	/* Prepare for Tx DMA channel stop */
@@ -3240,12 +3212,11 @@ static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 
		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);



	/* Disable each Tx DMA channel */

	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->tx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->tx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);

	}

}
@@ -3277,16 +3248,14 @@ static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, 


static void xgbe_enable_rx(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int reg_val, i;



	/* Enable each Rx DMA channel */

	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->rx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->rx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);

	}



	/* Enable each Rx queue */
@@ -3304,7 +3273,6 @@ static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 


static void xgbe_disable_rx(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	/* Disable MAC Rx */
@@ -3321,27 +3289,24 @@ static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 
	XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);



	/* Disable each Rx DMA channel */

	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->rx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->rx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);

	}

}



static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	/* Enable each Tx DMA channel */

	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->tx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->tx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);

	}



	/* Enable MAC Tx */
@@ -3350,7 +3315,6 @@ static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 


static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	/* Prepare for Tx DMA channel stop */
@@ -3361,42 +3325,37 @@ static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 
	XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);



	/* Disable each Tx DMA channel */

	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->tx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->tx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);

	}

}



static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	/* Enable each Rx DMA channel */

	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->rx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->rx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);

	}

}



static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)

{

	struct xgbe_channel *channel;

	unsigned int i;



	/* Disable each Rx DMA channel */

	channel = pdata->channel;

	for (i = 0; i < pdata->channel_count; i++, channel++) {

		if (!channel->rx_ring)

	for (i = 0; i < pdata->channel_count; i++) {

		if (!pdata->channel[i]->rx_ring)

			break;



		XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);

		XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);

	}

}
@@ -3420,9 +3379,7 @@ static int xgbe_init(struct xgbe_prv_data *pdata) 
	xgbe_config_dma_bus(pdata);

	xgbe_config_dma_cache(pdata);

	xgbe_config_osp_mode(pdata);

	xgbe_config_pblx8(pdata);

	xgbe_config_tx_pbl_val(pdata);

	xgbe_config_rx_pbl_val(pdata);

	xgbe_config_pbl_val(pdata);

	xgbe_config_rx_coalesce(pdata);

	xgbe_config_tx_coalesce(pdata);

	xgbe_config_rx_buffer_size(pdata);
@@ -3550,13 +3507,6 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 
	/* For TX DMA Operating on Second Frame config */

	hw_if->config_osp_mode = xgbe_config_osp_mode;



	/* For RX and TX PBL config */

	hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;

	hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;

	hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;

	hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;

	hw_if->config_pblx8 = xgbe_config_pblx8;



	/* For MMC statistics support */

	hw_if->tx_mmc_int = xgbe_tx_mmc_int;

	hw_if->rx_mmc_int = xgbe_rx_mmc_int;

drivers/net/ethernet/amd/xgbe/xgbe-drv.c

+159 −86

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/amd/xgbe/xgbe-i2c.c

+25 −5
Original line number Diff line number Diff line
@@ -274,13 +274,16 @@ static void xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata, 
		XI2C_IOREAD(pdata, IC_CLR_STOP_DET);

}



static irqreturn_t xgbe_i2c_isr(int irq, void *data)

static void xgbe_i2c_isr_task(unsigned long data)

{

	struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;

	struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;

	unsigned int isr;



	isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);

	if (!isr)

		goto reissue_check;



	netif_dbg(pdata, intr, pdata->netdev,

		  "I2C interrupt received: status=%#010x\n", isr);
@@ -308,6 +311,21 @@ out: 
	if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))

		complete(&pdata->i2c_complete);



reissue_check:

	/* Reissue interrupt if status is not clear */

	if (pdata->vdata->irq_reissue_support)

		XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 2);

}



static irqreturn_t xgbe_i2c_isr(int irq, void *data)

{

	struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;



	if (pdata->isr_as_tasklet)

		tasklet_schedule(&pdata->tasklet_i2c);

	else

		xgbe_i2c_isr_task((unsigned long)pdata);



	return IRQ_HANDLED;

}
@@ -349,12 +367,11 @@ static void xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr) 
	XI2C_IOWRITE(pdata, IC_TAR, addr);

}



static irqreturn_t xgbe_i2c_combined_isr(int irq, struct xgbe_prv_data *pdata)

static irqreturn_t xgbe_i2c_combined_isr(struct xgbe_prv_data *pdata)

{

	if (!XI2C_IOREAD(pdata, IC_RAW_INTR_STAT))

		return IRQ_HANDLED;

	xgbe_i2c_isr_task((unsigned long)pdata);



	return xgbe_i2c_isr(irq, pdata);

	return IRQ_HANDLED;

}



static int xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op)
@@ -445,6 +462,9 @@ static int xgbe_i2c_start(struct xgbe_prv_data *pdata) 


	/* If we have a separate I2C irq, enable it */

	if (pdata->dev_irq != pdata->i2c_irq) {

		tasklet_init(&pdata->tasklet_i2c, xgbe_i2c_isr_task,

			     (unsigned long)pdata);



		ret = devm_request_irq(pdata->dev, pdata->i2c_irq,

				       xgbe_i2c_isr, 0, pdata->i2c_name,

				       pdata);

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