Commit 64f929d8 authored by Anson Huang's avatar Anson Huang Committed by Stephen Boyd
Browse files

ARM: dts: imx7: correct enet ipg clock



ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK
rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus
clock.

Based on Andy Duan's patch from the NXP kernel tree.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9c7150da
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+1 −1
Original line number Diff line number Diff line
@@ -120,7 +120,7 @@
			<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
		clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
			<&clks IMX7D_ENET_AXI_ROOT_CLK>,
			<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
			<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+1 −1
Original line number Diff line number Diff line
@@ -1091,7 +1091,7 @@
					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
				clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
					<&clks IMX7D_ENET_AXI_ROOT_CLK>,
					<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,