Commit 64e3bbc7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:
 - a short branch of OMAP fixes that we didn't merge before the window
   opened.
 - a small cleanup that sorts the rk3288 dts entries properly
 - a build fix due to a reference to a removed DT node on exynos

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: exynos5420: remove disp_pd
  ARM: EXYNOS: Fix suspend/resume sequences
  ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi
  ARM: OMAP3: Fix coding style problems in arch/arm/mach-omap2/control.c
  ARM: OMAP3: Fix choice of omap3_restore_es function in OMAP34XX rev3.1.2 case.
  ARM: OMAP2+: clock: allow omap2_dpll_round_rate() to round to next-lowest rate
parents 91384758 ee34fb97

arch/arm/boot/dts/exynos5420.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -525,7 +525,6 @@ 
		compatible = "samsung,exynos5410-mipi-dsi";

		reg = <0x14500000 0x10000>;

		interrupts = <0 82 0>;

		samsung,power-domain = <&disp_pd>;

		phys = <&mipi_phy 1>;

		phy-names = "dsim";

		clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;

arch/arm/boot/dts/rk3288.dtsi

+20 −20
Original line number Diff line number Diff line
@@ -195,6 +195,26 @@ 
		status = "disabled";

	};



	usb_host0_ehci: usb@ff500000 {

		compatible = "generic-ehci";

		reg = <0xff500000 0x100>;

		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_USBHOST0>;

		clock-names = "usbhost";

		status = "disabled";

	};



	/* NOTE: ohci@ff520000 doesn't actually work on hardware */



	usb_hsic: usb@ff5c0000 {

		compatible = "generic-ehci";

		reg = <0xff5c0000 0x100>;

		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_HSIC>;

		clock-names = "usbhost";

		status = "disabled";

	};



	i2c0: i2c@ff650000 {

		compatible = "rockchip,rk3288-i2c";

		reg = <0xff650000 0x1000>;
@@ -251,26 +271,6 @@ 
		status = "disabled";

	};



	usb_host0_ehci: usb@ff500000 {

		compatible = "generic-ehci";

		reg = <0xff500000 0x100>;

		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_USBHOST0>;

		clock-names = "usbhost";

		status = "disabled";

	};



	/* NOTE: ohci@ff520000 doesn't actually work on hardware */



	usb_hsic: usb@ff5c0000 {

		compatible = "generic-ehci";

		reg = <0xff5c0000 0x100>;

		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru HCLK_HSIC>;

		clock-names = "usbhost";

		status = "disabled";

	};



	gic: interrupt-controller@ffc01000 {

		compatible = "arm,gic-400";

		interrupt-controller;

arch/arm/mach-exynos/pm.c

+76 −87
Original line number Diff line number Diff line
@@ -114,26 +114,6 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) 
#define S5P_CHECK_AFTR  0xFCBA0D10

#define S5P_CHECK_SLEEP 0x00000BAD



/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */

static void exynos_set_wakeupmask(long mask)

{

	pmu_raw_writel(mask, S5P_WAKEUP_MASK);

}



static void exynos_cpu_set_boot_vector(long flags)

{

	__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);

	__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);

}



void exynos_enter_aftr(void)

{

	exynos_set_wakeupmask(0x0000ff3e);

	exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);

	/* Set value of power down register for aftr mode */

	exynos_sys_powerdown_conf(SYS_AFTR);

}



/* For Cortex-A9 Diagnostic and Power control register */

static unsigned int save_arm_register[2];
@@ -173,6 +153,82 @@ static void exynos_cpu_restore_register(void) 
		      : "cc");

}



static void exynos_pm_central_suspend(void)

{

	unsigned long tmp;



	/* Setting Central Sequence Register for power down mode */

	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);

	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;

	pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

}



static int exynos_pm_central_resume(void)

{

	unsigned long tmp;



	/*

	 * If PMU failed while entering sleep mode, WFI will be

	 * ignored by PMU and then exiting cpu_do_idle().

	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically

	 * in this situation.

	 */

	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);

	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {

		tmp |= S5P_CENTRAL_LOWPWR_CFG;

		pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

		/* clear the wakeup state register */

		pmu_raw_writel(0x0, S5P_WAKEUP_STAT);

		/* No need to perform below restore code */

		return -1;

	}



	return 0;

}



/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */

static void exynos_set_wakeupmask(long mask)

{

	pmu_raw_writel(mask, S5P_WAKEUP_MASK);

}



static void exynos_cpu_set_boot_vector(long flags)

{

	__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);

	__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);

}



static int exynos_aftr_finisher(unsigned long flags)

{

	exynos_set_wakeupmask(0x0000ff3e);

	exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);

	/* Set value of power down register for aftr mode */

	exynos_sys_powerdown_conf(SYS_AFTR);

	cpu_do_idle();



	return 1;

}



void exynos_enter_aftr(void)

{

	cpu_pm_enter();



	exynos_pm_central_suspend();

	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)

		exynos_cpu_save_register();



	cpu_suspend(0, exynos_aftr_finisher);



	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {

		scu_enable(S5P_VA_SCU);

		exynos_cpu_restore_register();

	}



	exynos_pm_central_resume();



	cpu_pm_exit();

}



static int exynos_cpu_suspend(unsigned long arg)

{

#ifdef CONFIG_CACHE_L2X0
@@ -217,16 +273,6 @@ static void exynos_pm_prepare(void) 
	pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);

}



static void exynos_pm_central_suspend(void)

{

	unsigned long tmp;



	/* Setting Central Sequence Register for power down mode */

	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);

	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;

	pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

}



static int exynos_pm_suspend(void)

{

	unsigned long tmp;
@@ -244,29 +290,6 @@ static int exynos_pm_suspend(void) 
	return 0;

}



static int exynos_pm_central_resume(void)

{

	unsigned long tmp;



	/*

	 * If PMU failed while entering sleep mode, WFI will be

	 * ignored by PMU and then exiting cpu_do_idle().

	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically

	 * in this situation.

	 */

	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);

	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {

		tmp |= S5P_CENTRAL_LOWPWR_CFG;

		pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

		/* clear the wakeup state register */

		pmu_raw_writel(0x0, S5P_WAKEUP_STAT);

		/* No need to perform below restore code */

		return -1;

	}



	return 0;

}



static void exynos_pm_resume(void)

{

	if (exynos_pm_central_resume())
@@ -369,44 +392,10 @@ static const struct platform_suspend_ops exynos_suspend_ops = { 
	.valid		= suspend_valid_only_mem,

};



static int exynos_cpu_pm_notifier(struct notifier_block *self,

				  unsigned long cmd, void *v)

{

	int cpu = smp_processor_id();



	switch (cmd) {

	case CPU_PM_ENTER:

		if (cpu == 0) {

			exynos_pm_central_suspend();

			if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)

				exynos_cpu_save_register();

		}

		break;



	case CPU_PM_EXIT:

		if (cpu == 0) {

			if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {

				scu_enable(S5P_VA_SCU);

				exynos_cpu_restore_register();

			}

			exynos_pm_central_resume();

		}

		break;

	}



	return NOTIFY_OK;

}



static struct notifier_block exynos_cpu_pm_notifier_block = {

	.notifier_call = exynos_cpu_pm_notifier,

};



void __init exynos_pm_init(void)

{

	u32 tmp;



	cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);



	/* Platform-specific GIC callback */

	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;

arch/arm/mach-omap2/clkt_dpll.c

+21 −7
Original line number Diff line number Diff line
@@ -285,10 +285,13 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 
{

	struct clk_hw_omap *clk = to_clk_hw_omap(hw);

	int m, n, r, scaled_max_m;

	int min_delta_m = INT_MAX, min_delta_n = INT_MAX;

	unsigned long scaled_rt_rp;

	unsigned long new_rate = 0;

	struct dpll_data *dd;

	unsigned long ref_rate;

	long delta;

	long prev_min_delta = LONG_MAX;

	const char *clk_name;



	if (!clk || !clk->dpll_data)
@@ -334,23 +337,34 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 
		if (r == DPLL_MULT_UNDERFLOW)

			continue;



		/* skip rates above our target rate */

		delta = target_rate - new_rate;

		if (delta < 0)

			continue;



		if (delta < prev_min_delta) {

			prev_min_delta = delta;

			min_delta_m = m;

			min_delta_n = n;

		}



		pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",

			 clk_name, m, n, new_rate);



		if (target_rate == new_rate) {

			dd->last_rounded_m = m;

			dd->last_rounded_n = n;

			dd->last_rounded_rate = target_rate;

		if (delta == 0)

			break;

	}

	}



	if (target_rate != new_rate) {

	if (prev_min_delta == LONG_MAX) {

		pr_debug("clock: %s: cannot round to rate %lu\n",

			 clk_name, target_rate);

		return ~0;

	}



	return target_rate;

	dd->last_rounded_m = min_delta_m;

	dd->last_rounded_n = min_delta_n;

	dd->last_rounded_rate = target_rate - prev_min_delta;



	return dd->last_rounded_rate;

}

arch/arm/mach-omap2/control.c

+3 −3
Original line number Diff line number Diff line
@@ -280,6 +280,7 @@ void omap3_clear_scratchpad_contents(void) 
	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;

	void __iomem *v_addr;

	u32 offset = 0;



	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);

	if (omap3xxx_prm_clear_global_cold_reset()) {

		for ( ; offset <= max_offset; offset += 0x4)
@@ -309,7 +310,8 @@ void omap3_save_scratchpad_contents(void) 
		scratchpad_contents.public_restore_ptr =

			virt_to_phys(omap3_restore_3630);

	else if (omap_rev() != OMAP3430_REV_ES3_0 &&

					omap_rev() != OMAP3430_REV_ES3_1)

					omap_rev() != OMAP3430_REV_ES3_1 &&

					omap_rev() != OMAP3430_REV_ES3_1_2)

		scratchpad_contents.public_restore_ptr =

			virt_to_phys(omap3_restore);

	else
@@ -463,7 +465,6 @@ void omap3_control_save_context(void) 
	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);

	control_context.padconf_sys_nirq =

		omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);

	return;

}



void omap3_control_restore_context(void)
@@ -521,7 +522,6 @@ void omap3_control_restore_context(void) 
	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);

	omap_ctrl_writel(control_context.padconf_sys_nirq,

			 OMAP343X_CONTROL_PADCONF_SYSNIRQ);

	return;

}



void omap3630_ctrl_disable_rta(void)

CRA Git | Maintained and supported by SUSTech CRA and CCSE