Commit 64cc3ea9 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

ARM: dts: exynos: Use defines for MCT interrupt GIC SPI/PPI specifier 



Replace hard-coded number with appropriate define for GIC SPI or PPI
specifier in interrupt.  This makes code easier to read.  No expected
functionality change.

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 04d6fe24

arch/arm/boot/dts/exynos4210.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -111,12 +111,12 @@ 
			reg = <0x10050000 0x800>;

			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;

			clock-names = "fin_pll", "mct";

			interrupts-extended = <&gic 0 57 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 69 IRQ_TYPE_LEVEL_HIGH>,

			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

					      <&combiner 12 6>,

					      <&combiner 12 7>,

					      <&gic 0 42 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 48 IRQ_TYPE_LEVEL_HIGH>;

					      <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

		};



		watchdog: watchdog@10060000 {

arch/arm/boot/dts/exynos4412.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -248,11 +248,11 @@ 
			reg = <0x10050000 0x800>;

			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;

			clock-names = "fin_pll", "mct";

			interrupts-extended = <&gic 0 57 IRQ_TYPE_LEVEL_HIGH>,

			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

					      <&combiner 12 5>,

					      <&combiner 12 6>,

					      <&combiner 12 7>,

					      <&gic 1 12 IRQ_TYPE_LEVEL_HIGH>;

					      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;

		};



		watchdog: watchdog@10060000 {

arch/arm/boot/dts/exynos5250.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -242,8 +242,8 @@ 
					      <&combiner 23 4>,

					      <&combiner 25 2>,

					      <&combiner 25 3>,

					      <&gic 0 120 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 121 IRQ_TYPE_LEVEL_HIGH>;

					      <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

		};



		pinctrl_0: pinctrl@11400000 {

arch/arm/boot/dts/exynos54xx.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -80,14 +80,14 @@ 
					      <&combiner 23 4>,

					      <&combiner 25 2>,

					      <&combiner 25 3>,

					      <&gic 0 120 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 121 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 122 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 123 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 128 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 129 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 130 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic 0 131 IRQ_TYPE_LEVEL_HIGH>;

					      <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

					      <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

		};



		watchdog: watchdog@101d0000 {

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