Commit 64c9247b authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Stephen Boyd
Browse files

clk: at91: clk-generated: pass the id of changeable parent at registration 



Pass the ID of changeable parent at registration. This will allow
the scalability of this clock driver with regards to the changeable
parent ID for versions of this IP where changeable parent is not the
last one in the parents list (e.g. SAMA7G5). With this the clock flags
are set to zero in case we have no changeable parent. Also in
clk_generated_best_diff() the *best_diff variable is check against
tmp_diff variable using ">=" operator instead of ">" so that in case
the requested frequency could be obtained using fix parents + gck
dividers but the clock also supports changeable parent to be able
to force the usage of the changeable parent.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-11-git-send-email-claudiu.beznea@microchip.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 42324d95

drivers/clk/at91/clk-generated.c

+14 −12
Original line number Diff line number Diff line
@@ -18,8 +18,6 @@ 


#define GENERATED_MAX_DIV	255



#define GCK_INDEX_DT_AUDIO_PLL	5



struct clk_generated {

	struct clk_hw hw;

	struct regmap *regmap;
@@ -29,7 +27,7 @@ struct clk_generated { 
	u32 gckdiv;

	const struct clk_pcr_layout *layout;

	u8 parent_id;

	bool audio_pll_allowed;

	int chg_pid;

};



#define to_clk_generated(hw) \
@@ -109,7 +107,7 @@ static void clk_generated_best_diff(struct clk_rate_request *req, 
		tmp_rate = parent_rate / div;

	tmp_diff = abs(req->rate - tmp_rate);



	if (*best_diff < 0 || *best_diff > tmp_diff) {

	if (*best_diff < 0 || *best_diff >= tmp_diff) {

		*best_rate = tmp_rate;

		*best_diff = tmp_diff;

		req->best_parent_rate = parent_rate;
@@ -129,7 +127,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw, 
	int i;

	u32 div;



	for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {

	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {

		if (gck->chg_pid == i)

			continue;



		parent = clk_hw_get_parent_by_index(hw, i);

		if (!parent)

			continue;
@@ -161,10 +162,10 @@ static int clk_generated_determine_rate(struct clk_hw *hw, 
	 * that the only clks able to modify gck rate are those of audio IPs.

	 */



	if (!gck->audio_pll_allowed)

	if (gck->chg_pid < 0)

		goto end;



	parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);

	parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);

	if (!parent)

		goto end;
@@ -272,8 +273,8 @@ struct clk_hw * __init 
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,

			    const struct clk_pcr_layout *layout,

			    const char *name, const char **parent_names,

			    u8 num_parents, u8 id, bool pll_audio,

			    const struct clk_range *range)

			    u8 num_parents, u8 id,

			    const struct clk_range *range, int chg_pid)

{

	struct clk_generated *gck;

	struct clk_init_data init;
@@ -288,15 +289,16 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, 
	init.ops = &generated_ops;

	init.parent_names = parent_names;

	init.num_parents = num_parents;

	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |

		CLK_SET_RATE_PARENT;

	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;

	if (chg_pid >= 0)

		init.flags |= CLK_SET_RATE_PARENT;



	gck->id = id;

	gck->hw.init = &init;

	gck->regmap = regmap;

	gck->lock = lock;

	gck->range = *range;

	gck->audio_pll_allowed = pll_audio;

	gck->chg_pid = chg_pid;

	gck->layout = layout;



	clk_generated_startup(gck);

drivers/clk/at91/dt-compat.c

+5 −3
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ 


#define SYSTEM_MAX_ID		31



#define GCK_INDEX_DT_AUDIO_PLL	5



#ifdef CONFIG_HAVE_AT91_AUDIO_PLL

static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)

{
@@ -135,7 +137,7 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np) 
		return;



	for_each_child_of_node(np, gcknp) {

		bool pll_audio = false;

		int chg_pid = INT_MIN;



		if (of_property_read_u32(gcknp, "reg", &id))

			continue;
@@ -152,12 +154,12 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np) 
		if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&

		    (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||

		     id == GCK_ID_CLASSD))

			pll_audio = true;

			chg_pid = GCK_INDEX_DT_AUDIO_PLL;



		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,

						 &dt_pcr_layout, name,

						 parent_names, num_parents,

						 id, pll_audio, &range);

						 id, &range, chg_pid);

		if (IS_ERR(hw))

			continue;

drivers/clk/at91/pmc.h

+2 −2
Original line number Diff line number Diff line
@@ -122,8 +122,8 @@ struct clk_hw * __init 
at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,

			    const struct clk_pcr_layout *layout,

			    const char *name, const char **parent_names,

			    u8 num_parents, u8 id, bool pll_audio,

			    const struct clk_range *range);

			    u8 num_parents, u8 id,

			    const struct clk_range *range, int chg_pid);



struct clk_hw * __init

at91_clk_register_h32mx(struct regmap *regmap, const char *name,

drivers/clk/at91/sam9x60.c

+1 −2
Original line number Diff line number Diff line
@@ -290,8 +290,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) 
						 sam9x60_gck[i].n,

						 parent_names, 6,

						 sam9x60_gck[i].id,

						 false,

						 &sam9x60_gck[i].r);

						 &sam9x60_gck[i].r, INT_MIN);

		if (IS_ERR(hw))

			goto err_free;

drivers/clk/at91/sama5d2.c

+15 −16
Original line number Diff line number Diff line
@@ -116,21 +116,20 @@ static const struct { 
	char *n;

	u8 id;

	struct clk_range r;

	bool pll;

	int chg_pid;

} sama5d2_gck[] = {

	{ .n = "sdmmc0_gclk", .id = 31, },

	{ .n = "sdmmc1_gclk", .id = 32, },

	{ .n = "tcb0_gclk",   .id = 35, .r = { .min = 0, .max = 83000000 }, },

	{ .n = "tcb1_gclk",   .id = 36, .r = { .min = 0, .max = 83000000 }, },

	{ .n = "pwm_gclk",    .id = 38, .r = { .min = 0, .max = 83000000 }, },

	{ .n = "isc_gclk",    .id = 46, },

	{ .n = "pdmic_gclk",  .id = 48, },

	{ .n = "i2s0_gclk",   .id = 54, .pll = true },

	{ .n = "i2s1_gclk",   .id = 55, .pll = true },

	{ .n = "can0_gclk",   .id = 56, .r = { .min = 0, .max = 80000000 }, },

	{ .n = "can1_gclk",   .id = 57, .r = { .min = 0, .max = 80000000 }, },

	{ .n = "classd_gclk", .id = 59, .r = { .min = 0, .max = 100000000 },

	  .pll = true },

	{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },

	{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },

	{ .n = "tcb0_gclk",   .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },

	{ .n = "tcb1_gclk",   .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },

	{ .n = "pwm_gclk",    .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },

	{ .n = "isc_gclk",    .id = 46, .chg_pid = INT_MIN, },

	{ .n = "pdmic_gclk",  .id = 48, .chg_pid = INT_MIN, },

	{ .n = "i2s0_gclk",   .id = 54, .chg_pid = 5, },

	{ .n = "i2s1_gclk",   .id = 55, .chg_pid = 5, },

	{ .n = "can0_gclk",   .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },

	{ .n = "can1_gclk",   .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },

	{ .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, },

};



static const struct clk_programmable_layout sama5d2_programmable_layout = {
@@ -324,8 +323,8 @@ static void __init sama5d2_pmc_setup(struct device_node *np) 
						 sama5d2_gck[i].n,

						 parent_names, 6,

						 sama5d2_gck[i].id,

						 sama5d2_gck[i].pll,

						 &sama5d2_gck[i].r);

						 &sama5d2_gck[i].r,

						 sama5d2_gck[i].chg_pid);

		if (IS_ERR(hw))

			goto err_free;

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