Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev (64b853aa) · Commits · 戴 / test

drivers/ata/ahci.c

+111 −48

Original line number	Original line	Diff line number	Diff line
	@@ -46,7 +46,7 @@
	#include <linux/libata.h>		#include <linux/libata.h>

	#define DRV_NAME "ahci"		#define DRV_NAME "ahci"
	#define DRV_VERSION "2.2"		#define DRV_VERSION "2.3"


	enum {		enum {
	@@ -54,7 +54,7 @@ enum {
	AHCI_MAX_PORTS = 32,		AHCI_MAX_PORTS = 32,
	AHCI_MAX_SG = 168, /* hardware max is 64K */		AHCI_MAX_SG = 168, /* hardware max is 64K */
	AHCI_DMA_BOUNDARY = 0xffffffff,		AHCI_DMA_BOUNDARY = 0xffffffff,
	AHCI_USE_CLUSTERING = 0,		AHCI_USE_CLUSTERING = 1,
	AHCI_MAX_CMDS = 32,		AHCI_MAX_CMDS = 32,
	AHCI_CMD_SZ = 32,		AHCI_CMD_SZ = 32,
	AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,		AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
	@@ -81,6 +81,7 @@ enum {
	board_ahci_vt8251 = 2,		board_ahci_vt8251 = 2,
	board_ahci_ign_iferr = 3,		board_ahci_ign_iferr = 3,
	board_ahci_sb600 = 4,		board_ahci_sb600 = 4,
			board_ahci_mv = 5,

	/* global controller registers */		/* global controller registers */
	HOST_CAP = 0x00, /* host capabilities */		HOST_CAP = 0x00, /* host capabilities */
	@@ -171,6 +172,8 @@ enum {
	AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */		AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
	AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */		AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
	AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */		AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
			AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
			AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */

	AHCI_FLAG_COMMON = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|		AHCI_FLAG_COMMON = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	ATA_FLAG_MMIO \| ATA_FLAG_PIO_DMA \|		ATA_FLAG_MMIO \| ATA_FLAG_PIO_DMA \|
	@@ -228,9 +231,12 @@ static void ahci_thaw(struct ata_port *ap);
	static void ahci_error_handler(struct ata_port *ap);		static void ahci_error_handler(struct ata_port *ap);
	static void ahci_vt8251_error_handler(struct ata_port *ap);		static void ahci_vt8251_error_handler(struct ata_port *ap);
	static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);		static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
			static int ahci_port_resume(struct ata_port *ap);
			static unsigned int ahci_fill_sg(struct ata_queued_cmd qc, void cmd_tbl);
			static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
			u32 opts);
	#ifdef CONFIG_PM		#ifdef CONFIG_PM
	static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);		static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
	static int ahci_port_resume(struct ata_port *ap);
	static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);		static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
	static int ahci_pci_device_resume(struct pci_dev *pdev);		static int ahci_pci_device_resume(struct pci_dev *pdev);
	#endif		#endif
	@@ -327,14 +333,14 @@ static const struct ata_port_info ahci_port_info[] = {
	{		{
	.flags = AHCI_FLAG_COMMON,		.flags = AHCI_FLAG_COMMON,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.udma_mask = 0x7f, /* udma0-6 ; FIXME */		.udma_mask = ATA_UDMA6,
	.port_ops = &ahci_ops,		.port_ops = &ahci_ops,
	},		},
	/* board_ahci_pi */		/* board_ahci_pi */
	{		{
	.flags = AHCI_FLAG_COMMON \| AHCI_FLAG_HONOR_PI,		.flags = AHCI_FLAG_COMMON \| AHCI_FLAG_HONOR_PI,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.udma_mask = 0x7f, /* udma0-6 ; FIXME */		.udma_mask = ATA_UDMA6,
	.port_ops = &ahci_ops,		.port_ops = &ahci_ops,
	},		},
	/* board_ahci_vt8251 */		/* board_ahci_vt8251 */
	@@ -342,14 +348,14 @@ static const struct ata_port_info ahci_port_info[] = {
	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_HRST_TO_RESUME \|		.flags = AHCI_FLAG_COMMON \| ATA_FLAG_HRST_TO_RESUME \|
	AHCI_FLAG_NO_NCQ,		AHCI_FLAG_NO_NCQ,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.udma_mask = 0x7f, /* udma0-6 ; FIXME */		.udma_mask = ATA_UDMA6,
	.port_ops = &ahci_vt8251_ops,		.port_ops = &ahci_vt8251_ops,
	},		},
	/* board_ahci_ign_iferr */		/* board_ahci_ign_iferr */
	{		{
	.flags = AHCI_FLAG_COMMON \| AHCI_FLAG_IGN_IRQ_IF_ERR,		.flags = AHCI_FLAG_COMMON \| AHCI_FLAG_IGN_IRQ_IF_ERR,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.udma_mask = 0x7f, /* udma0-6 ; FIXME */		.udma_mask = ATA_UDMA6,
	.port_ops = &ahci_ops,		.port_ops = &ahci_ops,
	},		},
	/* board_ahci_sb600 */		/* board_ahci_sb600 */
	@@ -358,7 +364,19 @@ static const struct ata_port_info ahci_port_info[] = {
	AHCI_FLAG_IGN_SERR_INTERNAL \|		AHCI_FLAG_IGN_SERR_INTERNAL \|
	AHCI_FLAG_32BIT_ONLY,		AHCI_FLAG_32BIT_ONLY,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.udma_mask = 0x7f, /* udma0-6 ; FIXME */		.udma_mask = ATA_UDMA6,
			.port_ops = &ahci_ops,
			},
			/* board_ahci_mv */
			{
			.sht = &ahci_sht,
			.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
			ATA_FLAG_MMIO \| ATA_FLAG_PIO_DMA \|
			ATA_FLAG_SKIP_D2H_BSY \| AHCI_FLAG_HONOR_PI \|
			AHCI_FLAG_NO_NCQ \| AHCI_FLAG_NO_MSI \|
			AHCI_FLAG_MV_PATA,
			.pio_mask = 0x1f, /* pio0-4 */
			.udma_mask = ATA_UDMA6,
	.port_ops = &ahci_ops,		.port_ops = &ahci_ops,
	},		},
	};		};
	@@ -456,6 +474,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
	{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */		{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
	{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */		{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */

			/* Marvell */
			{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */

	/* Generic, PCI class code for AHCI */		/* Generic, PCI class code for AHCI */
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,		{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },		PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
	@@ -481,11 +502,17 @@ static inline int ahci_nr_ports(u32 cap)
	return (cap & 0x1f) + 1;		return (cap & 0x1f) + 1;
	}		}

	static inline void __iomem ahci_port_base(struct ata_port ap)		static inline void __iomem __ahci_port_base(struct ata_host host,
			unsigned int port_no)
	{		{
	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];		void __iomem *mmio = host->iomap[AHCI_PCI_BAR];

	return mmio + 0x100 + (ap->port_no * 0x80);		return mmio + 0x100 + (port_no * 0x80);
			}

			static inline void __iomem ahci_port_base(struct ata_port ap)
			{
			return __ahci_port_base(ap->host, ap->port_no);
	}		}

	/**		/**
	@@ -535,6 +562,20 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
	hpriv->saved_port_map = port_map;		hpriv->saved_port_map = port_map;
	}		}

			/*
			* Temporary Marvell 6145 hack: PATA port presence
			* is asserted through the standard AHCI port
			* presence register, as bit 4 (counting from 0)
			*/
			if (pi->flags & AHCI_FLAG_MV_PATA) {
			dev_printk(KERN_ERR, &pdev->dev,
			"MV_AHCI HACK: port_map %x -> %x\n",
			hpriv->port_map,
			hpriv->port_map & 0xf);

			port_map &= 0xf;
			}

	/* cross check port_map and cap.n_ports */		/* cross check port_map and cap.n_ports */
	if (pi->flags & AHCI_FLAG_HONOR_PI) {		if (pi->flags & AHCI_FLAG_HONOR_PI) {
	u32 tmp_port_map = port_map;		u32 tmp_port_map = port_map;
	@@ -740,7 +781,7 @@ static void ahci_power_down(struct ata_port *ap)
	}		}
	#endif		#endif

	static void ahci_init_port(struct ata_port *ap)		static void ahci_start_port(struct ata_port *ap)
	{		{
	/* enable FIS reception */		/* enable FIS reception */
	ahci_start_fis_rx(ap);		ahci_start_fis_rx(ap);
	@@ -814,20 +855,13 @@ static int ahci_reset_controller(struct ata_host *host)
	return 0;		return 0;
	}		}

	static void ahci_init_controller(struct ata_host *host)		static void ahci_port_init(struct pci_dev pdev, struct ata_port ap,
			int port_no, void __iomem *mmio,
			void __iomem *port_mmio)
	{		{
	struct pci_dev *pdev = to_pci_dev(host->dev);
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
	int i, rc;
	u32 tmp;

	for (i = 0; i < host->n_ports; i++) {
	struct ata_port *ap = host->ports[i];
	void __iomem *port_mmio = ahci_port_base(ap);
	const char *emsg = NULL;		const char *emsg = NULL;
			int rc;
	if (ata_port_is_dummy(ap))		u32 tmp;
	continue;

	/* make sure port is not active */		/* make sure port is not active */
	rc = ahci_deinit_port(ap, &emsg);		rc = ahci_deinit_port(ap, &emsg);
	@@ -846,7 +880,37 @@ static void ahci_init_controller(struct ata_host *host)
	if (tmp)		if (tmp)
	writel(tmp, port_mmio + PORT_IRQ_STAT);		writel(tmp, port_mmio + PORT_IRQ_STAT);

	writel(1 << i, mmio + HOST_IRQ_STAT);		writel(1 << port_no, mmio + HOST_IRQ_STAT);
			}

			static void ahci_init_controller(struct ata_host *host)
			{
			struct pci_dev *pdev = to_pci_dev(host->dev);
			void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
			int i;
			void __iomem *port_mmio;
			u32 tmp;

			if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
			port_mmio = __ahci_port_base(host, 4);

			writel(0, port_mmio + PORT_IRQ_MASK);

			/* clear port IRQ */
			tmp = readl(port_mmio + PORT_IRQ_STAT);
			VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
			if (tmp)
			writel(tmp, port_mmio + PORT_IRQ_STAT);
			}

			for (i = 0; i < host->n_ports; i++) {
			struct ata_port *ap = host->ports[i];

			port_mmio = ahci_port_base(ap);
			if (ata_port_is_dummy(ap))
			continue;

			ahci_port_init(pdev, ap, i, mmio, port_mmio);
	}		}

	tmp = readl(mmio + HOST_CTL);		tmp = readl(mmio + HOST_CTL);
	@@ -1232,7 +1296,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
	ata_port_abort(ap);		ata_port_abort(ap);
	}		}

	static void ahci_host_intr(struct ata_port *ap)		static void ahci_port_intr(struct ata_port *ap)
	{		{
	void __iomem *port_mmio = ap->ioaddr.cmd_addr;		void __iomem *port_mmio = ap->ioaddr.cmd_addr;
	struct ata_eh_info *ehi = &ap->eh_info;		struct ata_eh_info *ehi = &ap->eh_info;
	@@ -1358,7 +1422,7 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance)

	ap = host->ports[i];		ap = host->ports[i];
	if (ap) {		if (ap) {
	ahci_host_intr(ap);		ahci_port_intr(ap);
	VPRINTK("port %u\n", i);		VPRINTK("port %u\n", i);
	} else {		} else {
	VPRINTK("port %u (no irq)\n", i);		VPRINTK("port %u (no irq)\n", i);
	@@ -1466,7 +1530,7 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
	ahci_power_down(ap);		ahci_power_down(ap);
	else {		else {
	ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);		ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
	ahci_init_port(ap);		ahci_start_port(ap);
	}		}

	return rc;		return rc;
	@@ -1475,7 +1539,7 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
	static int ahci_port_resume(struct ata_port *ap)		static int ahci_port_resume(struct ata_port *ap)
	{		{
	ahci_power_up(ap);		ahci_power_up(ap);
	ahci_init_port(ap);		ahci_start_port(ap);

	return 0;		return 0;
	}		}
	@@ -1573,13 +1637,8 @@ static int ahci_port_start(struct ata_port *ap)

	ap->private_data = pp;		ap->private_data = pp;

	/* power up port */		/* engage engines, captain */
	ahci_power_up(ap);		return ahci_port_resume(ap);

	/* initialize port */
	ahci_init_port(ap);

	return 0;
	}		}

	static void ahci_port_stop(struct ata_port *ap)		static void ahci_port_stop(struct ata_port *ap)
	@@ -1724,7 +1783,7 @@ static int ahci_init_one(struct pci_dev pdev, const struct pci_device_id ent)
	if (rc)		if (rc)
	return rc;		return rc;

	if (pci_enable_msi(pdev))		if ((pi.flags & AHCI_FLAG_NO_MSI) \|\| pci_enable_msi(pdev))
	pci_intx(pdev, 1);		pci_intx(pdev, 1);

	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);		hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	@@ -1745,14 +1804,18 @@ static int ahci_init_one(struct pci_dev pdev, const struct pci_device_id ent)
	host->private_data = hpriv;		host->private_data = hpriv;

	for (i = 0; i < host->n_ports; i++) {		for (i = 0; i < host->n_ports; i++) {
	if (hpriv->port_map & (1 << i)) {
	struct ata_port *ap = host->ports[i];		struct ata_port *ap = host->ports[i];
	void __iomem *port_mmio = ahci_port_base(ap);		void __iomem *port_mmio = ahci_port_base(ap);

			/* standard SATA port setup */
			if (hpriv->port_map & (1 << i)) {
	ap->ioaddr.cmd_addr = port_mmio;		ap->ioaddr.cmd_addr = port_mmio;
	ap->ioaddr.scr_addr = port_mmio + PORT_SCR;		ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
	} else		}
	host->ports[i]->ops = &ata_dummy_port_ops;
			/* disabled/not-implemented port */
			else
			ap->ops = &ata_dummy_port_ops;
	}		}

	/* initialize adapter */		/* initialize adapter */

drivers/ata/ata_generic.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -143,10 +143,10 @@ static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id
	u16 command;		u16 command;
	static const struct ata_port_info info = {		static const struct ata_port_info info = {
	.sht = &generic_sht,		.sht = &generic_sht,
	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,		.flags = ATA_FLAG_SLAVE_POSS,
	.pio_mask = 0x1f,		.pio_mask = 0x1f,
	.mwdma_mask = 0x07,		.mwdma_mask = 0x07,
	.udma_mask = 0x3f,		.udma_mask = ATA_UDMA5,
	.port_ops = &generic_port_ops		.port_ops = &generic_port_ops
	};		};
	const struct ata_port_info *ppi[] = { &info, NULL };		const struct ata_port_info *ppi[] = { &info, NULL };

drivers/ata/ata_piix.c

+24 −11

Original line number	Original line	Diff line number	Diff line
	@@ -200,6 +200,8 @@ static const struct pci_device_id piix_pci_tbl[] = {
	/* ICH7/7-R (i945, i975) UDMA 100*/		/* ICH7/7-R (i945, i975) UDMA 100*/
	{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },		{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
	{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },		{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
			/* ICH8 Mobile PATA Controller */
			{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },

	/* NOTE: The following PCI ids must be kept in sync with the		/* NOTE: The following PCI ids must be kept in sync with the
	* list in drivers/pci/quirks.c.		* list in drivers/pci/quirks.c.
	@@ -495,7 +497,7 @@ static struct ata_port_info piix_port_info[] = {
	.flags = PIIX_SATA_FLAGS,		.flags = PIIX_SATA_FLAGS,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.mwdma_mask = 0x07, /* mwdma0-2 */		.mwdma_mask = 0x07, /* mwdma0-2 */
	.udma_mask = 0x7f, /* udma0-6 */		.udma_mask = ATA_UDMA6,
	.port_ops = &piix_sata_ops,		.port_ops = &piix_sata_ops,
	},		},

	@@ -505,7 +507,7 @@ static struct ata_port_info piix_port_info[] = {
	.flags = PIIX_SATA_FLAGS \| PIIX_FLAG_SCR,		.flags = PIIX_SATA_FLAGS \| PIIX_FLAG_SCR,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.mwdma_mask = 0x07, /* mwdma0-2 */		.mwdma_mask = 0x07, /* mwdma0-2 */
	.udma_mask = 0x7f, /* udma0-6 */		.udma_mask = ATA_UDMA6,
	.port_ops = &piix_sata_ops,		.port_ops = &piix_sata_ops,
	},		},

	@@ -516,7 +518,7 @@ static struct ata_port_info piix_port_info[] = {
	PIIX_FLAG_AHCI,		PIIX_FLAG_AHCI,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.mwdma_mask = 0x07, /* mwdma0-2 */		.mwdma_mask = 0x07, /* mwdma0-2 */
	.udma_mask = 0x7f, /* udma0-6 */		.udma_mask = ATA_UDMA6,
	.port_ops = &piix_sata_ops,		.port_ops = &piix_sata_ops,
	},		},

	@@ -527,7 +529,7 @@ static struct ata_port_info piix_port_info[] = {
	PIIX_FLAG_AHCI,		PIIX_FLAG_AHCI,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.mwdma_mask = 0x07, /* mwdma0-2 */		.mwdma_mask = 0x07, /* mwdma0-2 */
	.udma_mask = 0x7f, /* udma0-6 */		.udma_mask = ATA_UDMA6,
	.port_ops = &piix_sata_ops,		.port_ops = &piix_sata_ops,
	},		},

	@@ -538,7 +540,7 @@ static struct ata_port_info piix_port_info[] = {
	PIIX_FLAG_AHCI,		PIIX_FLAG_AHCI,
	.pio_mask = 0x1f, /* pio0-4 */		.pio_mask = 0x1f, /* pio0-4 */
	.mwdma_mask = 0x07, /* mwdma0-2 */		.mwdma_mask = 0x07, /* mwdma0-2 */
	.udma_mask = 0x7f, /* udma0-6 */		.udma_mask = ATA_UDMA6,
	.port_ops = &piix_sata_ops,		.port_ops = &piix_sata_ops,
	},		},

	@@ -685,8 +687,14 @@ static void piix_set_piomode (struct ata_port ap, struct ata_device adev)
	if (adev->class == ATA_DEV_ATA)		if (adev->class == ATA_DEV_ATA)
	control \|= 4; /* PPE enable */		control \|= 4; /* PPE enable */

			/* PIO configuration clears DTE unconditionally. It will be
			* programmed in set_dmamode which is guaranteed to be called
			* after set_piomode if any DMA mode is available.
			*/
	pci_read_config_word(dev, master_port, &master_data);		pci_read_config_word(dev, master_port, &master_data);
	if (is_slave) {		if (is_slave) {
			/* clear TIME1\|IE1\|PPE1\|DTE1 */
			master_data &= 0xff0f;
	/* Enable SITRE (seperate slave timing register) */		/* Enable SITRE (seperate slave timing register) */
	master_data \|= 0x4000;		master_data \|= 0x4000;
	/* enable PPE1, IE1 and TIME1 as needed */		/* enable PPE1, IE1 and TIME1 as needed */
	@@ -694,12 +702,14 @@ static void piix_set_piomode (struct ata_port ap, struct ata_device adev)
	pci_read_config_byte(dev, slave_port, &slave_data);		pci_read_config_byte(dev, slave_port, &slave_data);
	slave_data &= (ap->port_no ? 0x0f : 0xf0);		slave_data &= (ap->port_no ? 0x0f : 0xf0);
	/* Load the timing nibble for this slave */		/* Load the timing nibble for this slave */
	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << (ap->port_no ? 4 : 0);		slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1])
			<< (ap->port_no ? 4 : 0);
	} else {		} else {
	/* Master keeps the bits in a different format */		/* clear ISP\|RCT\|TIME0\|IE0\|PPE0\|DTE0 */
	master_data &= 0xccf8;		master_data &= 0xccf0;
	/* Enable PPE, IE and TIME as appropriate */		/* Enable PPE, IE and TIME as appropriate */
	master_data \|= control;		master_data \|= control;
			/* load ISP and RCT */
	master_data \|=		master_data \|=
	(timings[pio][0] << 12) \|		(timings[pio][0] << 12) \|
	(timings[pio][1] << 8);		(timings[pio][1] << 8);
	@@ -816,7 +826,7 @@ static void do_pata_set_dmamode (struct ata_port ap, struct ata_device adev, i
	master_data &= 0xFF4F; /* Mask out IORDY\|TIME1\|DMAONLY */		master_data &= 0xFF4F; /* Mask out IORDY\|TIME1\|DMAONLY */
	master_data \|= control << 4;		master_data \|= control << 4;
	pci_read_config_byte(dev, 0x44, &slave_data);		pci_read_config_byte(dev, 0x44, &slave_data);
	slave_data &= (0x0F + 0xE1 * ap->port_no);		slave_data &= (ap->port_no ? 0x0f : 0xf0);
	/* Load the matching timing */		/* Load the matching timing */
	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << (ap->port_no ? 4 : 0);		slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << (ap->port_no ? 4 : 0);
	pci_write_config_byte(dev, 0x44, slave_data);		pci_write_config_byte(dev, 0x44, slave_data);
	@@ -828,9 +838,12 @@ static void do_pata_set_dmamode (struct ata_port ap, struct ata_device adev, i
	(timings[pio][0] << 12) \|		(timings[pio][0] << 12) \|
	(timings[pio][1] << 8);		(timings[pio][1] << 8);
	}		}

			if (ap->udma_mask) {
	udma_enable &= ~(1 << devid);		udma_enable &= ~(1 << devid);
	pci_write_config_word(dev, master_port, master_data);		pci_write_config_word(dev, master_port, master_data);
	}		}
			}
	/* Don't scribble on 0x48 if the controller does not support UDMA */		/* Don't scribble on 0x48 if the controller does not support UDMA */
	if (ap->udma_mask)		if (ap->udma_mask)
	pci_write_config_byte(dev, 0x48, udma_enable);		pci_write_config_byte(dev, 0x48, udma_enable);

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