MIPS: OCTEON: irq: add CIB and other fixes (64b139f9) · Commits · 戴 / test

- Use of_irq_init() to initialize interrupt controllers - Get rid of some unlikely() - Add CIB to support SATA and other interrupts - Add support for CIU SUM2 interrupt sources Signed-off-by:

David Daney <david.daney@cavium.com> Signed-off-by:

Leonid Rosenboim <lrosenboim@caviumnetworks.com> Signed-off-by:

Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by:

Peter Swain <peter.swain@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8947/ Signed-off-by:

Ralf Baechle <ralf@linux-mips.org>

Documentation/devicetree/bindings/mips/cavium/cib.txt

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Original line number	Diff line number	Diff line
		* Cavium Interrupt Bus widget

		Properties:
		- compatible: "cavium,octeon-7130-cib"

		Compatibility with cn70XX SoCs.

		- interrupt-controller: This is an interrupt controller.

		- reg: Two elements consisting of the addresses of the RAW and EN
		registers of the CIB block

		- cavium,max-bits: The index (zero based) of the highest numbered bit
		in the CIB block.

		- interrupt-parent: Always the CIU on the SoC.

		- interrupts: The CIU line to which the CIB block is connected.

		- #interrupt-cells: Must be <2>. The first cell is the bit within the
		CIB. The second cell specifies the triggering semantics of the
		line.

		Example:

		interrupt-controller@107000000e000 {
		compatible = "cavium,octeon-7130-cib";
		reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
		<0x10700 0x0000e100 0x0 0x8>; /* EN */
		cavium,max-bits = <23>;

		interrupt-controller;
		interrupt-parent = <&ciu>;
		interrupts = <1 24>;
		/* Interrupts are specified by two parts:
		* 1) Bit number in the CIB* registers
		* 2) Triggering (1 - edge rising
		* 2 - edge falling
		* 4 - level active high
		* 8 - level active low)
		*/
		#interrupt-cells = <2>;
		};

arch/mips/cavium-octeon/octeon-irq.c

+780 −269

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