Commit 64990a43 authored by Nicolin Chen's avatar Nicolin Chen Committed by Shawn Guo
Browse files

ARM: imx6q: Add pll4_audio_div to clock tree 



There's a pll4_audio_div clock, an extra divider for pll4, missing
in current clock tree, thus add it.

Signed-off-by: default avatarNicolin Chen <b42378@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 6886530b

Documentation/devicetree/bindings/clock/imx6q-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -215,6 +215,7 @@ clocks and IDs. 
	cko2      		200

	cko      		201

	vdoa      		202

	pll4_audio_div		203



Examples:

arch/arm/mach-imx/clk-imx6q.c

+5 −4
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; 
static const char *periph_sels[]	= { "periph_pre", "periph_clk2", };

static const char *periph2_sels[]	= { "periph2_pre", "periph2_clk2", };

static const char *axi_sels[]		= { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };

static const char *audio_sels[]	= { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };

static const char *audio_sels[]	= { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };

static const char *gpu_axi_sels[]	= { "axi", "ahb", };

static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };

static const char *gpu3d_core_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
@@ -196,7 +196,7 @@ static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di 
static const char *ipu2_di1_sels[]	= { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };

static const char *hsi_tx_sels[]	= { "pll3_120m", "pll2_pfd2_396m", };

static const char *pcie_axi_sels[]	= { "axi", "ahb", };

static const char *ssi_sels[]		= { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };

static const char *ssi_sels[]		= { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };

static const char *usdhc_sels[]	= { "pll2_pfd2_396m", "pll2_pfd0_352m", };

static const char *enfc_sels[]	= { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };

static const char *emi_sels[]		= { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
@@ -205,7 +205,7 @@ static const char *vdo_axi_sels[] = { "axi", "ahb", }; 
static const char *vpu_axi_sels[]	= { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };

static const char *cko1_sels[]	= { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",

				    "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",

				    "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };

				    "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };

static const char *cko2_sels[] = {

	"mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",

	"gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
@@ -251,7 +251,7 @@ enum mx6q_clks { 
	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,

	sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,

	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,

	spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max

	spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max

};



static struct clk *clk[clk_max];
@@ -359,6 +359,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	clk[twd]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);



	clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);

	clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);

	clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);

	clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);

CRA Git | Maintained and supported by SUSTech CRA and CCSE