Commit 6471bd74 authored by Wambui Karuga's avatar Wambui Karuga Committed by Jani Nikula
Browse files

drm/i915/psr: automatic conversion to drm_device based logging macros. 



Converts instances of the printk based logging macros to the struct
drm_device based logging macros in i915/display/intel_psr.c using the
following coccinelle script that transforms based on the existence of a
drm_i915_private device pointer:
@@
identifier fn, T;
@@

fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}

@@
identifier fn, T;
@@

fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}

Checkpatch warnings were addressed manually.

Signed-off-by: default avatarWambui Karuga <wambui.karugax@gmail.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200130083229.12889-11-wambui.karugax@gmail.com
parent 6efb1b7d

drivers/gpu/drm/i915/display/intel_psr.c

+77 −51
Original line number Diff line number Diff line
@@ -174,13 +174,15 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) 


	if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {

		dev_priv->psr.last_entry_attempt = time_ns;

		DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",

		drm_dbg_kms(&dev_priv->drm,

			    "[transcoder %s] PSR entry attempt in 2 vblanks\n",

			    transcoder_name(cpu_transcoder));

	}



	if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {

		dev_priv->psr.last_exit = time_ns;

		DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",

		drm_dbg_kms(&dev_priv->drm,

			    "[transcoder %s] PSR exit completed\n",

			    transcoder_name(cpu_transcoder));



		if (INTEL_GEN(dev_priv) >= 9) {
@@ -197,7 +199,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) 
	if (psr_iir & EDP_PSR_ERROR(trans_shift)) {

		u32 val;



		DRM_WARN("[transcoder %s] PSR aux error\n",

		drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",

			 transcoder_name(cpu_transcoder));



		dev_priv->psr.irq_aux_error = true;
@@ -272,7 +274,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) 
		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);



	if (dev_priv->psr.dp) {

		DRM_WARN("More than one eDP panel found, PSR support should be extended\n");

		drm_warn(&dev_priv->drm,

			 "More than one eDP panel found, PSR support should be extended\n");

		return;

	}
@@ -281,16 +284,18 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) 


	if (!intel_dp->psr_dpcd[0])

		return;

	DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",

	drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",

		    intel_dp->psr_dpcd[0]);



	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {

		DRM_DEBUG_KMS("PSR support not currently available for this panel\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR support not currently available for this panel\n");

		return;

	}



	if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {

		DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");

		drm_dbg_kms(&dev_priv->drm,

			    "Panel lacks power state control, PSR cannot be enabled\n");

		return;

	}
@@ -318,7 +323,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) 
		 * GTC first.

		 */

		dev_priv->psr.sink_psr2_support = y_req && alpm;

		DRM_DEBUG_KMS("PSR2 %ssupported\n",

		drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",

			    dev_priv->psr.sink_psr2_support ? "" : "not ");



		if (dev_priv->psr.sink_psr2_support) {
@@ -588,7 +593,7 @@ static void tgl_dc5_idle_thread(struct work_struct *work) 
	if (delayed_work_pending(&dev_priv->psr.idle_work))

		goto unlock;



	DRM_DEBUG_KMS("DC5/6 idle thread\n");

	drm_dbg_kms(&dev_priv->drm, "DC5/6 idle thread\n");

	tgl_psr2_disable_dc3co(dev_priv);

unlock:

	mutex_unlock(&dev_priv->psr.lock);
@@ -646,7 +651,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
		return false;



	if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {

		DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n",

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not supported in transcoder %s\n",

			    transcoder_name(crtc_state->cpu_transcoder));

		return false;

	}
@@ -657,7 +663,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
	 * over PSR2.

	 */

	if (crtc_state->dsc.compression_enable) {

		DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 cannot be enabled since DSC is enabled\n");

		return false;

	}
@@ -676,14 +683,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
	}



	if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) {

		DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",

			    crtc_hdisplay, crtc_vdisplay,

			    psr_max_h, psr_max_v);

		return false;

	}



	if (crtc_state->pipe_bpp > max_bpp) {

		DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n",

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, pipe bpp %d > max supported %d\n",

			    crtc_state->pipe_bpp, max_bpp);

		return false;

	}
@@ -695,13 +704,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
	 * x granularity.

	 */

	if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {

		DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n",

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, hdisplay(%d) not multiple of %d\n",

			    crtc_hdisplay, dev_priv->psr.su_x_granularity);

		return false;

	}



	if (crtc_state->crc_enabled) {

		DRM_DEBUG_KMS("PSR2 not enabled because it would inhibit pipe CRC calculation\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled because it would inhibit pipe CRC calculation\n");

		return false;

	}
@@ -731,30 +742,35 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, 
	 * hardcoded to PORT_A

	 */

	if (dig_port->base.port != PORT_A) {

		DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR condition failed: Port not supported\n");

		return;

	}



	if (dev_priv->psr.sink_not_reliable) {

		DRM_DEBUG_KMS("PSR sink implementation is not reliable\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR sink implementation is not reliable\n");

		return;

	}



	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {

		DRM_DEBUG_KMS("PSR condition failed: Interlaced mode enabled\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR condition failed: Interlaced mode enabled\n");

		return;

	}



	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);

	if (psr_setup_time < 0) {

		DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",

		drm_dbg_kms(&dev_priv->drm,

			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",

			    intel_dp->psr_dpcd[1]);

		return;

	}



	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >

	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {

		DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",

		drm_dbg_kms(&dev_priv->drm,

			    "PSR condition failed: PSR setup time (%d us) too long\n",

			    psr_setup_time);

		return;

	}
@@ -877,11 +893,12 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, 
	}

	if (val) {

		dev_priv->psr.sink_not_reliable = true;

		DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR interruption error set, not enabling PSR\n");

		return;

	}



	DRM_DEBUG_KMS("Enabling PSR%s\n",

	drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",

		    dev_priv->psr.psr2_enabled ? "2" : "1");

	intel_psr_setup_vsc(intel_dp, crtc_state);

	intel_psr_enable_sink(intel_dp);
@@ -914,7 +931,7 @@ void intel_psr_enable(struct intel_dp *intel_dp, 
	mutex_lock(&dev_priv->psr.lock);



	if (!psr_global_enabled(dev_priv->psr.debug)) {

		DRM_DEBUG_KMS("PSR disabled by flag\n");

		drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");

		goto unlock;

	}
@@ -972,7 +989,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
	if (!dev_priv->psr.enabled)

		return;



	DRM_DEBUG_KMS("Disabling PSR%s\n",

	drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",

		    dev_priv->psr.psr2_enabled ? "2" : "1");



	intel_psr_exit(dev_priv);
@@ -988,7 +1005,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
	/* Wait till PSR is idle */

	if (intel_de_wait_for_clear(dev_priv, psr_status,

				    psr_status_mask, 2000))

		DRM_ERROR("Timed out waiting PSR idle state\n");

		drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");



	/* Disable PSR on Sink */

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
@@ -1156,7 +1173,8 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) 


	err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);

	if (err)

		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");

		drm_err(&dev_priv->drm,

			"Timed out waiting for PSR Idle for re-enable\n");



	/* After the unlocked wait, verify that PSR is still wanted! */

	mutex_lock(&dev_priv->psr.lock);
@@ -1220,7 +1238,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) 


	if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||

	    mode > I915_PSR_DEBUG_FORCE_PSR1) {

		DRM_DEBUG_KMS("Invalid debug mask %llx\n", val);

		drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);

		return -EINVAL;

	}
@@ -1476,14 +1494,15 @@ static void psr_alpm_check(struct intel_dp *intel_dp) 


	r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);

	if (r != 1) {

		DRM_ERROR("Error reading ALPM status\n");

		drm_err(&dev_priv->drm, "Error reading ALPM status\n");

		return;

	}



	if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {

		intel_psr_disable_locked(intel_dp);

		psr->sink_not_reliable = true;

		DRM_DEBUG_KMS("ALPM lock timeout error, disabling PSR\n");

		drm_dbg_kms(&dev_priv->drm,

			    "ALPM lock timeout error, disabling PSR\n");



		/* Clearing error */

		drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
@@ -1499,14 +1518,15 @@ static void psr_capability_changed_check(struct intel_dp *intel_dp) 


	r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);

	if (r != 1) {

		DRM_ERROR("Error reading DP_PSR_ESI\n");

		drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");

		return;

	}



	if (val & DP_PSR_CAPS_CHANGE) {

		intel_psr_disable_locked(intel_dp);

		psr->sink_not_reliable = true;

		DRM_DEBUG_KMS("Sink PSR capability changed, disabling PSR\n");

		drm_dbg_kms(&dev_priv->drm,

			    "Sink PSR capability changed, disabling PSR\n");



		/* Clearing it */

		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
@@ -1531,7 +1551,8 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) 
		goto exit;



	if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {

		DRM_ERROR("Error reading PSR status or error status\n");

		drm_err(&dev_priv->drm,

			"Error reading PSR status or error status\n");

		goto exit;

	}
@@ -1541,16 +1562,21 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) 
	}



	if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)

		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR sink internal error, disabling PSR\n");

	if (error_status & DP_PSR_RFB_STORAGE_ERROR)

		DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR RFB storage error, disabling PSR\n");

	if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)

		DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR VSC SDP uncorrectable error, disabling PSR\n");

	if (error_status & DP_PSR_LINK_CRC_ERROR)

		DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");

		drm_dbg_kms(&dev_priv->drm,

			    "PSR Link CRC error, disabling PSR\n");



	if (error_status & ~errors)

		DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",

		drm_err(&dev_priv->drm,

			"PSR_ERROR_STATUS unhandled errors %x\n",

			error_status & ~errors);

	/* clear status register */

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);

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