Commit 6467a71c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  drm/i915: Stop trying to use ACPI lid status to determine LVDS connection.
  drm/intel: fix up set_tiling for untiled->tiled transition
  drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.
  agp/intel: Don't do the chipset flush on Sandybridge.
  agp/intel: Respect the GTT size on Sandybridge for scratch page setup.
  drm/i915: fix small leak on overlay error path
  drm/i915: Avoid NULL deref in get_pages() unwind after error.
  drm/i915: Fix check with IS_GEN6
  drivers/gpu/drm/i915/intel_bios.c: fix continuation line formats
  drm/i915: Enable VS timer dispatch.
  drm/i915: Rename FBC_C3_IDLE to FBC_CTL_C3_IDLE to match other registers
  drm/i915: remove an unnecessary wait_request()
  drm/i915: Don't bother with the BKL for GEM ioctls.
parents 18020a0d 6e6c8228

drivers/char/agp/intel-agp.c

+31 −3
Original line number Diff line number Diff line
@@ -97,6 +97,9 @@ EXPORT_SYMBOL(intel_agp_enabled); 
#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)



#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)



#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
@@ -107,8 +110,7 @@ EXPORT_SYMBOL(intel_agp_enabled); 
		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \

		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)

		IS_SNB)



extern int agp_memory_reserved;
@@ -175,6 +177,10 @@ extern int agp_memory_reserved; 
#define SNB_GMCH_GMS_STOLEN_448M	(0xe << 3)

#define SNB_GMCH_GMS_STOLEN_480M	(0xf << 3)

#define SNB_GMCH_GMS_STOLEN_512M	(0x10 << 3)

#define SNB_GTT_SIZE_0M			(0 << 8)

#define SNB_GTT_SIZE_1M			(1 << 8)

#define SNB_GTT_SIZE_2M			(2 << 8)

#define SNB_GTT_SIZE_MASK		(3 << 8)



static const struct aper_size_info_fixed intel_i810_sizes[] =

{
@@ -1200,6 +1206,9 @@ static void intel_i9xx_setup_flush(void) 
	if (intel_private.ifp_resource.start)

		return;



	if (IS_SNB)

		return;



	/* setup a resource for this object */

	intel_private.ifp_resource.name = "Intel Flush Page";

	intel_private.ifp_resource.flags = IORESOURCE_MEM;
@@ -1438,6 +1447,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 


static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)

{

	u16 snb_gmch_ctl;



	switch (agp_bridge->dev->device) {

	case PCI_DEVICE_ID_INTEL_GM45_HB:

	case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB:
@@ -1449,9 +1460,26 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) 
	case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:

	case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:

	case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:

		*gtt_offset = *gtt_size = MB(2);

		break;

	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB:

	case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB:

		*gtt_offset = *gtt_size = MB(2);

		*gtt_offset = MB(2);



		pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);

		switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {

		default:

		case SNB_GTT_SIZE_0M:

			printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);

			*gtt_size = MB(0);

			break;

		case SNB_GTT_SIZE_1M:

			*gtt_size = MB(1);

			break;

		case SNB_GTT_SIZE_2M:

			*gtt_size = MB(2);

			break;

		}

		break;

	default:

		*gtt_offset = *gtt_size = KB(512);

drivers/gpu/drm/i915/i915_dma.c

+23 −23
Original line number Diff line number Diff line
@@ -1881,29 +1881,29 @@ struct drm_ioctl_desc i915_ioctls[] = { 
	DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),

	DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),

	DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),

	DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),

	DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),

	DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),

	DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),

	DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),

	DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW),

	DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW),

	DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),

	DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),

};



int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -139,12 +139,12 @@ const static struct intel_device_info intel_ironlake_m_info = { 


const static struct intel_device_info intel_sandybridge_d_info = {

	.is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_hotplug = 1,

	.has_hotplug = 1, .is_gen6 = 1,

};



const static struct intel_device_info intel_sandybridge_m_info = {

	.is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1,

	.has_hotplug = 1,

	.has_hotplug = 1, .is_gen6 = 1,

};



const static struct pci_device_id pciidlist[] = {

drivers/gpu/drm/i915/i915_drv.h

+2 −2
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ struct intel_device_info { 
	u8 is_g4x : 1;

	u8 is_pineview : 1;

	u8 is_ironlake : 1;

	u8 is_gen6 : 1;

	u8 has_fbc : 1;

	u8 has_rc6 : 1;

	u8 has_pipe_cxsr : 1;
@@ -1084,6 +1085,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)

#define IS_IRONLAKE(dev)	(INTEL_INFO(dev)->is_ironlake)

#define IS_I9XX(dev)		(INTEL_INFO(dev)->is_i9xx)

#define IS_GEN6(dev)		(INTEL_INFO(dev)->is_gen6)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)



#define IS_GEN3(dev)	(IS_I915G(dev) ||			\
@@ -1107,8 +1109,6 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 


#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)



#define IS_GEN6(dev)	((dev)->pci_device == 0x0102)



/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

 * rows, which changed the alignment requirements and fence programming.

 */

drivers/gpu/drm/i915/i915_gem.c

+17 −14
Original line number Diff line number Diff line
@@ -1466,9 +1466,6 @@ i915_gem_object_put_pages(struct drm_gem_object *obj) 
		obj_priv->dirty = 0;



	for (i = 0; i < page_count; i++) {

		if (obj_priv->pages[i] == NULL)

			break;



		if (obj_priv->dirty)

			set_page_dirty(obj_priv->pages[i]);
@@ -2227,11 +2224,6 @@ i915_gem_evict_something(struct drm_device *dev, int min_size) 
				seqno = i915_add_request(dev, NULL, obj->write_domain);

				if (seqno == 0)

					return -ENOMEM;



				ret = i915_wait_request(dev, seqno);

				if (ret)

					return ret;



				continue;

			}

		}
@@ -2256,7 +2248,6 @@ i915_gem_object_get_pages(struct drm_gem_object *obj, 
	struct address_space *mapping;

	struct inode *inode;

	struct page *page;

	int ret;



	if (obj_priv->pages_refcount++ != 0)

		return 0;
@@ -2279,11 +2270,9 @@ i915_gem_object_get_pages(struct drm_gem_object *obj, 
					   mapping_gfp_mask (mapping) |

					   __GFP_COLD |

					   gfpmask);

		if (IS_ERR(page)) {

			ret = PTR_ERR(page);

			i915_gem_object_put_pages(obj);

			return ret;

		}

		if (IS_ERR(page))

			goto err_pages;



		obj_priv->pages[i] = page;

	}
@@ -2291,6 +2280,15 @@ i915_gem_object_get_pages(struct drm_gem_object *obj, 
		i915_gem_object_do_bit_17_swizzle(obj);



	return 0;



err_pages:

	while (i--)

		page_cache_release(obj_priv->pages[i]);



	drm_free_large(obj_priv->pages);

	obj_priv->pages = NULL;

	obj_priv->pages_refcount--;

	return PTR_ERR(page);

}



static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
@@ -4730,6 +4728,11 @@ i915_gem_init_ringbuffer(struct drm_device *dev) 
			ring->space += ring->Size;

	}



	if (IS_I9XX(dev) && !IS_GEN3(dev)) {

		I915_WRITE(MI_MODE,

			   (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);

	}



	return 0;

}

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