Commit 6436beee authored by Julien Thierry's avatar Julien Thierry Committed by Will Deacon
Browse files

arm64: Fix single stepping in kernel traps 



Software Step exception is missing after stepping a trapped instruction.

Ensure SPSR.SS gets set to 0 after emulating/skipping a trapped instruction
before doing ERET.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarJulien Thierry <julien.thierry@arm.com>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
[will: replaced AARCH32_INSN_SIZE with 4]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent e28cc025

arch/arm64/include/asm/traps.h

+6 −0
Original line number Diff line number Diff line
@@ -37,6 +37,12 @@ void unregister_undef_hook(struct undef_hook *hook); 


void arm64_notify_segfault(struct pt_regs *regs, unsigned long addr);



/*

 * Move regs->pc to next instruction and do necessary setup before it

 * is executed.

 */

void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);



static inline int __in_irqentry_text(unsigned long ptr)

{

	return ptr >= (unsigned long)&__irqentry_text_start &&

arch/arm64/kernel/armv8_deprecated.c

+4 −4
Original line number Diff line number Diff line
@@ -431,7 +431,7 @@ ret: 
	pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",

			current->comm, (unsigned long)current->pid, regs->pc);



	regs->pc += 4;

	arm64_skip_faulting_instruction(regs, 4);

	return 0;



fault:
@@ -512,7 +512,7 @@ ret: 
	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",

			current->comm, (unsigned long)current->pid, regs->pc);



	regs->pc += 4;

	arm64_skip_faulting_instruction(regs, 4);

	return 0;

}
@@ -586,14 +586,14 @@ static int compat_setend_handler(struct pt_regs *regs, u32 big_endian) 
static int a32_setend_handler(struct pt_regs *regs, u32 instr)

{

	int rc = compat_setend_handler(regs, (instr >> 9) & 1);

	regs->pc += 4;

	arm64_skip_faulting_instruction(regs, 4);

	return rc;

}



static int t16_setend_handler(struct pt_regs *regs, u32 instr)

{

	int rc = compat_setend_handler(regs, (instr >> 3) & 1);

	regs->pc += 2;

	arm64_skip_faulting_instruction(regs, 2);

	return rc;

}

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -1296,7 +1296,7 @@ static int emulate_mrs(struct pt_regs *regs, u32 insn) 
	if (!rc) {

		dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);

		pt_regs_write_reg(regs, dst, val);

		regs->pc += 4;

		arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);

	}



	return rc;

arch/arm64/kernel/traps.c

+16 −5
Original line number Diff line number Diff line
@@ -293,6 +293,17 @@ void arm64_notify_die(const char *str, struct pt_regs *regs, 
	}

}



void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)

{

	regs->pc += size;



	/*

	 * If we were single stepping, we want to get the step exception after

	 * we return from the trap.

	 */

	user_fastforward_single_step(current);

}



static LIST_HEAD(undef_hook);

static DEFINE_RAW_SPINLOCK(undef_lock);
@@ -480,7 +491,7 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 
	if (ret)

		arm64_notify_segfault(regs, address);

	else

		regs->pc += 4;

		arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);

}



static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
@@ -490,7 +501,7 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) 


	pt_regs_write_reg(regs, rt, val);



	regs->pc += 4;

	arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);

}



static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
@@ -498,7 +509,7 @@ static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) 
	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;



	pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());

	regs->pc += 4;

	arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);

}



static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
@@ -506,7 +517,7 @@ static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) 
	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;



	pt_regs_write_reg(regs, rt, arch_timer_get_rate());

	regs->pc += 4;

	arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);

}



struct sys64_hook {
@@ -761,7 +772,7 @@ static int bug_handler(struct pt_regs *regs, unsigned int esr) 
	}



	/* If thread survives, skip over the BUG instruction and continue: */

	regs->pc += AARCH64_INSN_SIZE;	/* skip BRK and resume */

	arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);

	return DBG_HOOK_HANDLED;

}

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