Commit 640356a4 authored May 17, 2016 by Paul Burton Committed by Ralf Baechle May 28, 2016

MIPS: Clear Status IPL field when using EIC



When using an external interrupt controller (EIC) the interrupt mask
bits in the cop0 Status register are reused for the Interrupt Priority
Level, and any interrupts with a priority lower than the field will be
ignored. Clear the field to 0 by default such that all interrupts are
serviced. Without doing so we default to arbitrarily ignoring all or
some subset of interrupts.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com>
Tested-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: Joe Perches <joe@perches.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13272/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 6e4ad1b4

arch/mips/kernel/irq.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -54,6 +54,9 @@ void __init init_IRQ(void)
		for (i = 0; i < NR_IRQS; i++)
		irq_set_noprobe(i);

		if (cpu_has_veic)
		clear_c0_status(ST0_IM);

		arch_init_irq();
		}

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