clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support (63e05d93) · Commits · 戴 / test

Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

+24 −2

Original line number	Original line	Diff line number	Diff line
	@@ -2,6 +2,8 @@

	The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs		The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
	and several fixed ratio dividers.		and several fixed ratio dividers.
			The CPG also provides a Clock Domain for SoC devices, in combination with the
			CPG Module Stop (MSTP) Clocks.

	Required Properties:		Required Properties:

	@@ -20,10 +22,18 @@ Required Properties:
	- clock-output-names: The names of the clocks. Supported clocks are "main",		- clock-output-names: The names of the clocks. Supported clocks are "main",
	"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and		"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
	"adsp"		"adsp"
			- #power-domain-cells: Must be 0

			SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
			through an MSTP clock should refer to the CPG device node in their
			"power-domains" property, as documented by the generic PM domain bindings in
			Documentation/devicetree/bindings/power/power_domain.txt.

	Example
	-------		Examples
			--------

			- CPG device node:

	cpg_clocks: cpg_clocks@e6150000 {		cpg_clocks: cpg_clocks@e6150000 {
	compatible = "renesas,r8a7790-cpg-clocks",		compatible = "renesas,r8a7790-cpg-clocks",
	@@ -34,4 +44,16 @@ Example
	clock-output-names = "main", "pll0, "pll1", "pll3",		clock-output-names = "main", "pll0, "pll1", "pll3",
	"lb", "qspi", "sdh", "sd0", "sd1", "z",		"lb", "qspi", "sdh", "sd0", "sd1", "z",
	"rcan", "adsp";		"rcan", "adsp";
			#power-domain-cells = <0>;
			};


			- CPG/MSTP Clock Domain member device node:

			thermal@e61f0000 {
			compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
			reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
			interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
			power-domains = <&cpg_clocks>;
	};		};

drivers/clk/shmobile/clk-rcar-gen2.c

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -415,6 +415,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
	}		}

	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);		of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);

			cpg_mstp_add_clk_domain(np);
	}		}
	CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",		CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
	rcar_gen2_cpg_clocks_init);		rcar_gen2_cpg_clocks_init);

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