Commit 638d957b authored by H. Peter Anvin's avatar H. Peter Anvin
Browse files

x86, realmode: Change EFER to a single u64 field 



Change EFER to be a single u64 field instead of two u32 fields; change
the order to maintain alignment.  Note that on x86-64 cr4 is really
also a 64-bit quantity, although we can only set the low 32 bits from
the trampoline code since it is still executing in 32-bit mode at that
point.

Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
Cc: Jarkko Sakkinen <jarkko.sakkinen@intel.com>
parent 13712701

arch/x86/include/asm/realmode.h

+1 −2
Original line number Diff line number Diff line
@@ -35,9 +35,8 @@ struct trampoline_header { 
	u32 gdt_base;

#else

	u64 start;

	u64 efer;

	u32 cr4;

	u32 efer_low;

	u32 efer_high;

#endif

};

arch/x86/realmode/init.c

+3 −4
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ void __init setup_real_mode(void) 
	size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);

#ifdef CONFIG_X86_64

	u64 *trampoline_pgd;

	u32 efer_low, efer_high;

	u64 efer;

#endif



	/* Has to be in very low memory so we can execute real-mode AP code. */
@@ -70,9 +70,8 @@ void __init setup_real_mode(void) 
	 * Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR

	 * so we need to mask it out.

	 */

	rdmsr(MSR_EFER, efer_low, efer_high);

	trampoline_header->efer_low  = efer_low & ~EFER_LMA;

	trampoline_header->efer_high = efer_high;

	rdmsrl(MSR_EFER, efer);

	trampoline_header->efer = efer & ~EFER_LMA;



	trampoline_header->start = (u64) secondary_startup_64;

	trampoline_cr4_features = &trampoline_header->cr4;

arch/x86/realmode/rm/trampoline_64.S

+1 −1
Original line number Diff line number Diff line
@@ -146,8 +146,8 @@ GLOBAL(trampoline_pgd) .space PAGE_SIZE 
	.balign	8

GLOBAL(trampoline_header)

	tr_start:		.space	8

	GLOBAL(tr_cr4)		.space	4

	GLOBAL(tr_efer)		.space	8

	GLOBAL(tr_cr4)		.space	4

END(trampoline_header)



#include "trampoline_common.S"

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