spi: spi-fsl-dspi: Optimize dspi_setup_accel for lowest interrupt count (6365504d) · Commits · 戴 / test

Currently, a SPI transfer that is not multiple of the highest supported word width (e.g. 4 bytes) will be transmitted as follows (assume a 30-byte buffer transmitted through a 32-bit wide FIFO that is 32 bytes deep): - First 28 bytes are sent as 7 words of 32 bits each - Last 2 bytes are sent as 1 word of 16 bits size But if the dspi_setup_accel function had decided to use a lower oper_bits_per_word value (16 instead of 32), there would have been enough space in the TX FIFO to fit the entire buffer in one go (15 words of 16 bits each). What we're actually trying to avoid is mixing word sizes within the same run with the TX FIFO, since there is an erratum surrounding this, and invalid data might get transmitted. So this patch adds special cases for when the remaining length of the buffer can be sent in one go as 8-bit or 16-bit words, otherwise it falls back to the standard logic of sending as many bytes as possible at the highest oper_bits_per_word value possible. The benefit is that there will be one less CMDFQ/EOQ interrupt to service when the entire buffer is transmitted during a single go, and that will improve the overall latency of the transfer. Signed-off-by:

Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://lore.kernel.org/r/20200304220044.11193-11-olteanv@gmail.com Signed-off-by:

Mark Brown <broonie@kernel.org>

drivers/spi/spi-fsl-dspi.c

+25 −11

Original line number	Diff line number	Diff line
		@@ -775,20 +775,34 @@ static void dspi_fifo_read(struct fsl_dspi *dspi)
		static void dspi_setup_accel(struct fsl_dspi *dspi)
		{
		struct spi_transfer *xfer = dspi->cur_transfer;
		bool odd = !!(dspi->len & 1);

		/* No accel for frames not multiple of 8 bits at the moment */
		if (xfer->bits_per_word % 8)
		goto no_accel;

		if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
		dspi->oper_bits_per_word = 16;
		} else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
		dspi->oper_bits_per_word = 8;
		} else {
		/* Start off with maximum supported by hardware */
		if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
		dspi->oper_bits_per_word = 32;
		else
		dspi->oper_bits_per_word = 16;

		/* And go down only if the buffer can't be sent with words this big */
		/*
		* And go down only if the buffer can't be sent with
		* words this big
		*/
		do {
		if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
		break;

		dspi->oper_bits_per_word /= 2;
		} while (dspi->oper_bits_per_word > 8);
		}

		if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
		dspi->dev_to_host = dspi_8on32_dev_to_host;
		@@ -800,7 +814,7 @@ static void dspi_setup_accel(struct fsl_dspi *dspi)
		dspi->dev_to_host = dspi_16on32_dev_to_host;
		dspi->host_to_dev = dspi_16on32_host_to_dev;
		} else {
		/* No acceleration needed (8<N<=16 on 16, 16<N<=32 on 32) */
		no_accel:
		dspi->dev_to_host = dspi_native_dev_to_host;
		dspi->host_to_dev = dspi_native_host_to_dev;
		dspi->oper_bits_per_word = xfer->bits_per_word;

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