net: macb: use resolved link config in mac_link_up() (633e98a7) · Commits · 戴 / test

drivers/net/ethernet/cadence/macb.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -1200,7 +1200,6 @@ struct macb {
		unsigned int dma_burst_length;

		phy_interface_t phy_interface;
		int speed;

		/* AT91RM9200 transmit */
		struct sk_buff skb; / holds skb until xmit interrupt completes */

drivers/net/ethernet/cadence/macb_main.c

+29 −21

Original line number	Diff line number	Diff line
		@@ -571,37 +571,20 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode,

		old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);

		/* Clear all the bits we might set later */
		ctrl &= ~(MACB_BIT(SPD) \| MACB_BIT(FD) \| MACB_BIT(PAE));

		if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
		if (state->interface == PHY_INTERFACE_MODE_RMII)
		ctrl \|= MACB_BIT(RM9200_RMII);
		} else {
		ctrl &= ~(GEM_BIT(GBE) \| GEM_BIT(SGMIIEN) \| GEM_BIT(PCSSEL));

		/* We do not support MLO_PAUSE_RX yet */
		if (state->pause & MLO_PAUSE_TX)
		ctrl \|= MACB_BIT(PAE);
		ctrl &= ~(GEM_BIT(SGMIIEN) \| GEM_BIT(PCSSEL));

		if (state->interface == PHY_INTERFACE_MODE_SGMII)
		ctrl \|= GEM_BIT(SGMIIEN) \| GEM_BIT(PCSSEL);
		}

		if (state->speed == SPEED_1000)
		ctrl \|= GEM_BIT(GBE);
		else if (state->speed == SPEED_100)
		ctrl \|= MACB_BIT(SPD);

		if (state->duplex)
		ctrl \|= MACB_BIT(FD);

		/* Apply the new configuration, if any */
		if (old_ctrl ^ ctrl)
		macb_or_gem_writel(bp, NCFGR, ctrl);

		bp->speed = state->speed;

		spin_unlock_irqrestore(&bp->lock, flags);
		}

		@@ -635,10 +618,33 @@ static void macb_mac_link_up(struct phylink_config *config,
		struct net_device *ndev = to_net_dev(config->dev);
		struct macb *bp = netdev_priv(ndev);
		struct macb_queue *queue;
		unsigned long flags;
		unsigned int q;
		u32 ctrl;

		spin_lock_irqsave(&bp->lock, flags);

		ctrl = macb_or_gem_readl(bp, NCFGR);

		ctrl &= ~(MACB_BIT(SPD) \| MACB_BIT(FD));

		if (speed == SPEED_100)
		ctrl \|= MACB_BIT(SPD);

		if (duplex)
		ctrl \|= MACB_BIT(FD);

		if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
		macb_set_tx_clk(bp->tx_clk, bp->speed, ndev);
		ctrl &= ~(GEM_BIT(GBE) \| MACB_BIT(PAE));

		if (speed == SPEED_1000)
		ctrl \|= GEM_BIT(GBE);

		/* We do not support MLO_PAUSE_RX yet */
		if (tx_pause)
		ctrl \|= MACB_BIT(PAE);

		macb_set_tx_clk(bp->tx_clk, speed, ndev);

		/* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
		* cleared the pipeline and control registers.
		@@ -651,6 +657,10 @@ static void macb_mac_link_up(struct phylink_config *config,
		bp->rx_intr_mask \| MACB_TX_INT_FLAGS \| MACB_BIT(HRESP));
		}

		macb_or_gem_writel(bp, NCFGR, ctrl);

		spin_unlock_irqrestore(&bp->lock, flags);

		/* Enable Rx and Tx */
		macb_writel(bp, NCR, macb_readl(bp, NCR) \| MACB_BIT(RE) \| MACB_BIT(TE));

		@@ -4432,8 +4442,6 @@ static int macb_probe(struct platform_device *pdev)
		else
		bp->phy_interface = interface;

		bp->speed = SPEED_UNKNOWN;

		/* IP specific init */
		err = init(pdev);
		if (err)

Admin message