Commit 63207c37 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls 



clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.

Reported-by: default avatarkernel test robot <lkp@intel.com>
Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: default avatarKever Yang <kever.yang@rock-chips.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200914022225.23613-2-zhangqing@rock-chips.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 816e8725

drivers/clk/rockchip/clk-half-divider.c

+10 −8
Original line number Diff line number Diff line
@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, 
					  unsigned long flags,

					  spinlock_t *lock)

{

	struct clk *clk;

	struct clk_hw *hw;

	struct clk_mux *mux = NULL;

	struct clk_gate *gate = NULL;

	struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, 
		div_ops = &clk_half_divider_ops;

	}



	clk = clk_register_composite(NULL, name, parent_names, num_parents,

	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

				       mux ? &mux->hw : NULL, mux_ops,

				       div ? &div->hw : NULL, div_ops,

				       gate ? &gate->hw : NULL, gate_ops,

				       flags);

	if (IS_ERR(hw))

		goto err_div;



	return clk;

	return hw->clk;

err_div:

	kfree(gate);

err_gate:

	kfree(mux);

	return ERR_PTR(-ENOMEM);

	return ERR_CAST(hw);

}

drivers/clk/rockchip/clk.c

+30 −31
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, 
		u8 gate_shift, u8 gate_flags, unsigned long flags,

		spinlock_t *lock)

{

	struct clk *clk;

	struct clk_hw *hw;

	struct clk_mux *mux = NULL;

	struct clk_gate *gate = NULL;

	struct clk_divider *div = NULL;
@@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const char *name, 
						: &clk_divider_ops;

	}



	clk = clk_register_composite(NULL, name, parent_names, num_parents,

	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

				       mux ? &mux->hw : NULL, mux_ops,

				       div ? &div->hw : NULL, div_ops,

				       gate ? &gate->hw : NULL, gate_ops,

				       flags);



	if (IS_ERR(clk)) {

		ret = PTR_ERR(clk);

		goto err_composite;

	if (IS_ERR(hw)) {

		kfree(div);

		kfree(gate);

		return ERR_CAST(hw);

	}



	return clk;

err_composite:

	kfree(div);

	return hw->clk;

err_div:

	kfree(gate);

err_gate:
@@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch( 
		unsigned long flags, struct rockchip_clk_branch *child,

		spinlock_t *lock)

{

	struct clk_hw *hw;

	struct rockchip_clk_frac *frac;

	struct clk *clk;

	struct clk_gate *gate = NULL;

	struct clk_fractional_divider *div = NULL;

	const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
@@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch( 
	div->approximation = rockchip_fractional_approximation;

	div_ops = &clk_fractional_divider_ops;



	clk = clk_register_composite(NULL, name, parent_names, num_parents,

	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

				       NULL, NULL,

				       &div->hw, div_ops,

				       gate ? &gate->hw : NULL, gate_ops,

				       flags | CLK_SET_RATE_UNGATE);

	if (IS_ERR(clk)) {

	if (IS_ERR(hw)) {

		kfree(frac);

		return clk;

		return ERR_CAST(hw);

	}



	if (child) {
@@ -292,7 +290,7 @@ static struct clk *rockchip_clk_register_frac_branch( 
		mux_clk = clk_register(NULL, &frac_mux->hw);

		if (IS_ERR(mux_clk)) {

			kfree(frac);

			return clk;

			return mux_clk;

		}



		rockchip_clk_add_lookup(ctx, mux_clk, child->id);
@@ -301,7 +299,7 @@ static struct clk *rockchip_clk_register_frac_branch( 
		if (frac->mux_frac_idx >= 0) {

			pr_debug("%s: found fractional parent in mux at pos %d\n",

				 __func__, frac->mux_frac_idx);

			ret = clk_notifier_register(clk, &frac->clk_nb);

			ret = clk_notifier_register(hw->clk, &frac->clk_nb);

			if (ret)

				pr_err("%s: failed to register clock notifier for %s\n",

						__func__, name);
@@ -311,7 +309,7 @@ static struct clk *rockchip_clk_register_frac_branch( 
		}

	}



	return clk;

	return hw->clk;

}



static struct clk *rockchip_clk_register_factor_branch(const char *name,
@@ -320,7 +318,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name, 
		int gate_offset, u8 gate_shift, u8 gate_flags,

		unsigned long flags, spinlock_t *lock)

{

	struct clk *clk;

	struct clk_hw *hw;

	struct clk_gate *gate = NULL;

	struct clk_fixed_factor *fix = NULL;
@@ -349,16 +347,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name, 
	fix->mult = mult;

	fix->div = div;



	clk = clk_register_composite(NULL, name, parent_names, num_parents,

	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

				       NULL, NULL,

				       &fix->hw, &clk_fixed_factor_ops,

				       &gate->hw, &clk_gate_ops, flags);

	if (IS_ERR(clk)) {

	if (IS_ERR(hw)) {

		kfree(fix);

		kfree(gate);

		return ERR_CAST(hw);

	}



	return clk;

	return hw->clk;

}



struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,

CRA Git | Maintained and supported by SUSTech CRA and CCSE