Commit 62d00867 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (49 commits)
  MIPS: JZ4740: Set nand ecc offsets for the qi_lb60 board
  MIPS: JZ4740: qi_lb60: Add gpio-charger device
  MIPS: Wire up syncfs(2).
  MIPS: Hook up name_to_handle_at, open_by_handle_at and clock_adjtime syscalls.
  MIPS: VR41xx: Convert to new irq_chip functions
  MIPS: TXx9: Convert to new irq_chip functions
  MIPS: SNI: Convert to new irq_chip functions
  MIPS: Sibyte: Convert to new irq_chip functions
  MIPS: IP32: Convert to new irq_chip functions
  MIPS: IP27: Convert to new irq_chip functions
  MIPS: IP22/IP28: Convert to new irq_chip functions
  MIPS: RB532: Convert to new irq_chip functions
  MIPS: PowerTV: Convert to new irq_chip functions
  MIPS: PNX8550: Convert to new irq_chip functions
  MIPS: PNX83xx: Convert to new irq_chip functions
  MIPS: msp71xx: Convert to new irq_chip functions
  MIPS: Loongson: Convert to new irq_chip functions
  MIPS: Use generic show_interrupts()
  MIPS: SMTC: Cleanup the hook mess and use irq_data
  MIPS: SMTC: Use irq_data in smtc_forward_irq()
  ...
parents be4d250a c8fb4022

arch/mips/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ config MIPS 
	select HAVE_DMA_API_DEBUG

	select HAVE_GENERIC_HARDIRQS

	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_SHOW

	select HAVE_ARCH_JUMP_LABEL



menu "Machine selection"
@@ -862,6 +863,9 @@ config GPIO_TXX9 
config CFE

	bool



config ARCH_DMA_ADDR_T_64BIT

	def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT



config DMA_COHERENT

	bool

arch/mips/alchemy/common/irq.c

+50 −48
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
#include <asm/mach-pb1x00/pb1000.h>

#endif



static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);

static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type);



/* NOTE on interrupt priorities: The original writers of this code said:

 *
@@ -218,17 +218,17 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = { 
};





static void au1x_ic0_unmask(unsigned int irq_nr)

static void au1x_ic0_unmask(struct irq_data *d)

{

	unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;

	unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;

	au_writel(1 << bit, IC0_MASKSET);

	au_writel(1 << bit, IC0_WAKESET);

	au_sync();

}



static void au1x_ic1_unmask(unsigned int irq_nr)

static void au1x_ic1_unmask(struct irq_data *d)

{

	unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;

	unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;

	au_writel(1 << bit, IC1_MASKSET);

	au_writel(1 << bit, IC1_WAKESET);
@@ -236,31 +236,31 @@ static void au1x_ic1_unmask(unsigned int irq_nr) 
 * nowhere in the current kernel sources is it disabled.	--mlau

 */

#if defined(CONFIG_MIPS_PB1000)

	if (irq_nr == AU1000_GPIO15_INT)

	if (d->irq == AU1000_GPIO15_INT)

		au_writel(0x4000, PB1000_MDR); /* enable int */

#endif

	au_sync();

}



static void au1x_ic0_mask(unsigned int irq_nr)

static void au1x_ic0_mask(struct irq_data *d)

{

	unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;

	unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;

	au_writel(1 << bit, IC0_MASKCLR);

	au_writel(1 << bit, IC0_WAKECLR);

	au_sync();

}



static void au1x_ic1_mask(unsigned int irq_nr)

static void au1x_ic1_mask(struct irq_data *d)

{

	unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;

	unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;

	au_writel(1 << bit, IC1_MASKCLR);

	au_writel(1 << bit, IC1_WAKECLR);

	au_sync();

}



static void au1x_ic0_ack(unsigned int irq_nr)

static void au1x_ic0_ack(struct irq_data *d)

{

	unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;

	unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;



	/*

	 * This may assume that we don't get interrupts from
@@ -271,9 +271,9 @@ static void au1x_ic0_ack(unsigned int irq_nr) 
	au_sync();

}



static void au1x_ic1_ack(unsigned int irq_nr)

static void au1x_ic1_ack(struct irq_data *d)

{

	unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;

	unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;



	/*

	 * This may assume that we don't get interrupts from
@@ -284,9 +284,9 @@ static void au1x_ic1_ack(unsigned int irq_nr) 
	au_sync();

}



static void au1x_ic0_maskack(unsigned int irq_nr)

static void au1x_ic0_maskack(struct irq_data *d)

{

	unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;

	unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;



	au_writel(1 << bit, IC0_WAKECLR);

	au_writel(1 << bit, IC0_MASKCLR);
@@ -295,9 +295,9 @@ static void au1x_ic0_maskack(unsigned int irq_nr) 
	au_sync();

}



static void au1x_ic1_maskack(unsigned int irq_nr)

static void au1x_ic1_maskack(struct irq_data *d)

{

	unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;

	unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;



	au_writel(1 << bit, IC1_WAKECLR);

	au_writel(1 << bit, IC1_MASKCLR);
@@ -306,9 +306,9 @@ static void au1x_ic1_maskack(unsigned int irq_nr) 
	au_sync();

}



static int au1x_ic1_setwake(unsigned int irq, unsigned int on)

static int au1x_ic1_setwake(struct irq_data *d, unsigned int on)

{

	int bit = irq - AU1000_INTC1_INT_BASE;

	int bit = d->irq - AU1000_INTC1_INT_BASE;

	unsigned long wakemsk, flags;



	/* only GPIO 0-7 can act as wakeup source.  Fortunately these
@@ -336,28 +336,30 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 
 */

static struct irq_chip au1x_ic0_chip = {

	.name		= "Alchemy-IC0",

	.ack		= au1x_ic0_ack,

	.mask		= au1x_ic0_mask,

	.mask_ack	= au1x_ic0_maskack,

	.unmask		= au1x_ic0_unmask,

	.set_type	= au1x_ic_settype,

	.irq_ack	= au1x_ic0_ack,

	.irq_mask	= au1x_ic0_mask,

	.irq_mask_ack	= au1x_ic0_maskack,

	.irq_unmask	= au1x_ic0_unmask,

	.irq_set_type	= au1x_ic_settype,

};



static struct irq_chip au1x_ic1_chip = {

	.name		= "Alchemy-IC1",

	.ack		= au1x_ic1_ack,

	.mask		= au1x_ic1_mask,

	.mask_ack	= au1x_ic1_maskack,

	.unmask		= au1x_ic1_unmask,

	.set_type	= au1x_ic_settype,

	.set_wake	= au1x_ic1_setwake,

	.irq_ack	= au1x_ic1_ack,

	.irq_mask	= au1x_ic1_mask,

	.irq_mask_ack	= au1x_ic1_maskack,

	.irq_unmask	= au1x_ic1_unmask,

	.irq_set_type	= au1x_ic_settype,

	.irq_set_wake	= au1x_ic1_setwake,

};



static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)

static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)

{

	struct irq_chip *chip;

	unsigned long icr[6];

	unsigned int bit, ic;

	unsigned int bit, ic, irq = d->irq;

	irq_flow_handler_t handler = NULL;

	unsigned char *name = NULL;

	int ret;



	if (irq >= AU1000_INTC1_INT_BASE) {
@@ -387,47 +389,47 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) 
		au_writel(1 << bit, icr[5]);

		au_writel(1 << bit, icr[4]);

		au_writel(1 << bit, icr[0]);

		set_irq_chip_and_handler_name(irq, chip,

				handle_edge_irq, "riseedge");

		handler = handle_edge_irq;

		name = "riseedge";

		break;

	case IRQ_TYPE_EDGE_FALLING:	/* 0:1:0 */

		au_writel(1 << bit, icr[5]);

		au_writel(1 << bit, icr[1]);

		au_writel(1 << bit, icr[3]);

		set_irq_chip_and_handler_name(irq, chip,

				handle_edge_irq, "falledge");

		handler = handle_edge_irq;

		name = "falledge";

		break;

	case IRQ_TYPE_EDGE_BOTH:	/* 0:1:1 */

		au_writel(1 << bit, icr[5]);

		au_writel(1 << bit, icr[1]);

		au_writel(1 << bit, icr[0]);

		set_irq_chip_and_handler_name(irq, chip,

				handle_edge_irq, "bothedge");

		handler = handle_edge_irq;

		name = "bothedge";

		break;

	case IRQ_TYPE_LEVEL_HIGH:	/* 1:0:1 */

		au_writel(1 << bit, icr[2]);

		au_writel(1 << bit, icr[4]);

		au_writel(1 << bit, icr[0]);

		set_irq_chip_and_handler_name(irq, chip,

				handle_level_irq, "hilevel");

		handler = handle_level_irq;

		name = "hilevel";

		break;

	case IRQ_TYPE_LEVEL_LOW:	/* 1:1:0 */

		au_writel(1 << bit, icr[2]);

		au_writel(1 << bit, icr[1]);

		au_writel(1 << bit, icr[3]);

		set_irq_chip_and_handler_name(irq, chip,

				handle_level_irq, "lowlevel");

		handler = handle_level_irq;

		name = "lowlevel";

		break;

	case IRQ_TYPE_NONE:		/* 0:0:0 */

		au_writel(1 << bit, icr[5]);

		au_writel(1 << bit, icr[4]);

		au_writel(1 << bit, icr[3]);

		/* set at least chip so we can call set_irq_type() on it */

		set_irq_chip(irq, chip);

		break;

	default:

		ret = -EINVAL;

	}

	__irq_set_chip_handler_name_locked(d->irq, chip, handler, name);



	au_sync();



	return ret;
@@ -504,11 +506,11 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) 
	 */

	for (i = AU1000_INTC0_INT_BASE;

	     (i < AU1000_INTC0_INT_BASE + 32); i++)

		au1x_ic_settype(i, IRQ_TYPE_NONE);

		au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);



	for (i = AU1000_INTC1_INT_BASE;

	     (i < AU1000_INTC1_INT_BASE + 32); i++)

		au1x_ic_settype(i, IRQ_TYPE_NONE);

		au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);



	/*

	 * Initialize IC0, which is fixed per processor.
@@ -526,7 +528,7 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map) 
				au_writel(1 << bit, IC0_ASSIGNSET);

		}



		au1x_ic_settype(irq_nr, map->im_type);

		au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type);

		++map;

	}

arch/mips/alchemy/devboards/bcsr.c

+9 −9
Original line number Diff line number Diff line
@@ -97,26 +97,26 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) 
 * CPLD generates tons of spurious interrupts (at least on my DB1200).

 *	-- mlau

 */

static void bcsr_irq_mask(unsigned int irq_nr)

static void bcsr_irq_mask(struct irq_data *d)

{

	unsigned short v = 1 << (irq_nr - bcsr_csc_base);

	unsigned short v = 1 << (d->irq - bcsr_csc_base);

	__raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);

	__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);

	wmb();

}



static void bcsr_irq_maskack(unsigned int irq_nr)

static void bcsr_irq_maskack(struct irq_data *d)

{

	unsigned short v = 1 << (irq_nr - bcsr_csc_base);

	unsigned short v = 1 << (d->irq - bcsr_csc_base);

	__raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);

	__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);

	__raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT);	/* ack */

	wmb();

}



static void bcsr_irq_unmask(unsigned int irq_nr)

static void bcsr_irq_unmask(struct irq_data *d)

{

	unsigned short v = 1 << (irq_nr - bcsr_csc_base);

	unsigned short v = 1 << (d->irq - bcsr_csc_base);

	__raw_writew(v, bcsr_virt + BCSR_REG_INTSET);

	__raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);

	wmb();
@@ -124,9 +124,9 @@ static void bcsr_irq_unmask(unsigned int irq_nr) 


static struct irq_chip bcsr_irq_type = {

	.name		= "CPLD",

	.mask		= bcsr_irq_mask,

	.mask_ack	= bcsr_irq_maskack,

	.unmask		= bcsr_irq_unmask,

	.irq_mask	= bcsr_irq_mask,

	.irq_mask_ack	= bcsr_irq_maskack,

	.irq_unmask	= bcsr_irq_unmask,

};



void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)

arch/mips/ar7/irq.c

+21 −21
Original line number Diff line number Diff line
@@ -49,51 +49,51 @@ 


static int ar7_irq_base;



static void ar7_unmask_irq(unsigned int irq)

static void ar7_unmask_irq(struct irq_data *d)

{

	writel(1 << ((irq - ar7_irq_base) % 32),

	       REG(ESR_OFFSET(irq - ar7_irq_base)));

	writel(1 << ((d->irq - ar7_irq_base) % 32),

	       REG(ESR_OFFSET(d->irq - ar7_irq_base)));

}



static void ar7_mask_irq(unsigned int irq)

static void ar7_mask_irq(struct irq_data *d)

{

	writel(1 << ((irq - ar7_irq_base) % 32),

	       REG(ECR_OFFSET(irq - ar7_irq_base)));

	writel(1 << ((d->irq - ar7_irq_base) % 32),

	       REG(ECR_OFFSET(d->irq - ar7_irq_base)));

}



static void ar7_ack_irq(unsigned int irq)

static void ar7_ack_irq(struct irq_data *d)

{

	writel(1 << ((irq - ar7_irq_base) % 32),

	       REG(CR_OFFSET(irq - ar7_irq_base)));

	writel(1 << ((d->irq - ar7_irq_base) % 32),

	       REG(CR_OFFSET(d->irq - ar7_irq_base)));

}



static void ar7_unmask_sec_irq(unsigned int irq)

static void ar7_unmask_sec_irq(struct irq_data *d)

{

	writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));

	writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));

}



static void ar7_mask_sec_irq(unsigned int irq)

static void ar7_mask_sec_irq(struct irq_data *d)

{

	writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));

	writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));

}



static void ar7_ack_sec_irq(unsigned int irq)

static void ar7_ack_sec_irq(struct irq_data *d)

{

	writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));

	writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));

}



static struct irq_chip ar7_irq_type = {

	.name = "AR7",

	.unmask = ar7_unmask_irq,

	.mask = ar7_mask_irq,

	.ack = ar7_ack_irq

	.irq_unmask = ar7_unmask_irq,

	.irq_mask = ar7_mask_irq,

	.irq_ack = ar7_ack_irq

};



static struct irq_chip ar7_sec_irq_type = {

	.name = "AR7",

	.unmask = ar7_unmask_sec_irq,

	.mask = ar7_mask_sec_irq,

	.ack = ar7_ack_sec_irq,

	.irq_unmask = ar7_unmask_sec_irq,

	.irq_mask = ar7_mask_sec_irq,

	.irq_ack = ar7_ack_sec_irq,

};



static struct irqaction ar7_cascade_action = {

arch/mips/ath79/irq.c

+10 −14
Original line number Diff line number Diff line
@@ -62,13 +62,12 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) 
		spurious_interrupt();

}



static void ar71xx_misc_irq_unmask(unsigned int irq)

static void ar71xx_misc_irq_unmask(struct irq_data *d)

{

	unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;

	void __iomem *base = ath79_reset_base;

	u32 t;



	irq -= ATH79_MISC_IRQ_BASE;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
@@ -76,13 +75,12 @@ static void ar71xx_misc_irq_unmask(unsigned int irq) 
	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

}



static void ar71xx_misc_irq_mask(unsigned int irq)

static void ar71xx_misc_irq_mask(struct irq_data *d)

{

	unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;

	void __iomem *base = ath79_reset_base;

	u32 t;



	irq -= ATH79_MISC_IRQ_BASE;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
@@ -90,13 +88,12 @@ static void ar71xx_misc_irq_mask(unsigned int irq) 
	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);

}



static void ar724x_misc_irq_ack(unsigned int irq)

static void ar724x_misc_irq_ack(struct irq_data *d)

{

	unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;

	void __iomem *base = ath79_reset_base;

	u32 t;



	irq -= ATH79_MISC_IRQ_BASE;



	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);

	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
@@ -106,8 +103,8 @@ static void ar724x_misc_irq_ack(unsigned int irq) 


static struct irq_chip ath79_misc_irq_chip = {

	.name		= "MISC",

	.unmask		= ar71xx_misc_irq_unmask,

	.mask		= ar71xx_misc_irq_mask,

	.irq_unmask	= ar71xx_misc_irq_unmask,

	.irq_mask	= ar71xx_misc_irq_mask,

};



static void __init ath79_misc_irq_init(void)
@@ -119,15 +116,14 @@ static void __init ath79_misc_irq_init(void) 
	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);



	if (soc_is_ar71xx() || soc_is_ar913x())

		ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;

		ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;

	else if (soc_is_ar724x())

		ath79_misc_irq_chip.ack = ar724x_misc_irq_ack;

		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;

	else

		BUG();



	for (i = ATH79_MISC_IRQ_BASE;

	     i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {

		irq_desc[i].status = IRQ_DISABLED;

		set_irq_chip_and_handler(i, &ath79_misc_irq_chip,

					 handle_level_irq);

	}

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