Commit 62c2f3f6 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'uniphier-dt64-v4.10' of... 

Merge tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64

UniPhier ARM64 SoC DT updates for v4.10

- Switch CPU enable-method from spin-table to PSCI
- Add OPP tables to support generic cpufreq driver
- Misc fixes

* tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier

:
  arm64: dts: uniphier: make compatible of syscon nodes SoC-specific
  arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC
  arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
  arm64: dts: uniphier: increase register region size of sysctrl node
  arm64: dts: uniphier: switch over to PSCI enable method

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents a23ea957 fb28cef0

arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

+50 −9
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */

/memreserve/ 0x80000000 0x00080000;



/ {

	compatible = "socionext,uniphier-ld11";
@@ -70,19 +70,60 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x000>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			clocks = <&sys_clk 33>;

			enable-method = "psci";

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x001>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			clocks = <&sys_clk 33>;

			enable-method = "psci";

			operating-points-v2 = <&cluster0_opp>;

		};

	};



	cluster0_opp: opp_table {

		compatible = "operating-points-v2";

		opp-shared;



		opp@245000000 {

			opp-hz = /bits/ 64 <245000000>;

			clock-latency-ns = <300>;

		};

		opp@250000000 {

			opp-hz = /bits/ 64 <250000000>;

			clock-latency-ns = <300>;

		};

		opp@490000000 {

			opp-hz = /bits/ 64 <490000000>;

			clock-latency-ns = <300>;

		};

		opp@500000000 {

			opp-hz = /bits/ 64 <500000000>;

			clock-latency-ns = <300>;

		};

		opp@653334000 {

			opp-hz = /bits/ 64 <653334000>;

			clock-latency-ns = <300>;

		};

		opp@666667000 {

			opp-hz = /bits/ 64 <666667000>;

			clock-latency-ns = <300>;

		};

		opp@980000000 {

			opp-hz = /bits/ 64 <980000000>;

			clock-latency-ns = <300>;

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	clocks {

		refclk: ref {

			compatible = "fixed-clock";
@@ -233,7 +274,7 @@ 
		};



		perictrl@59820000 {

			compatible = "socionext,uniphier-perictrl",

			compatible = "socionext,uniphier-ld11-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;
@@ -282,7 +323,7 @@ 
		};



		mioctrl@5b3e0000 {

			compatible = "socionext,uniphier-mioctrl",

			compatible = "socionext,uniphier-ld11-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x5b3e0000 0x800>;
@@ -299,7 +340,7 @@ 
		};



		soc-glue@5f800000 {

			compatible = "socionext,uniphier-soc-glue",

			compatible = "socionext,uniphier-ld11-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;
@@ -320,7 +361,7 @@ 
		sysctrl@61840000 {

			compatible = "socionext,uniphier-ld11-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x4000>;

			reg = <0x61840000 0x10000>;



			sys_clk: clock {

				compatible = "socionext,uniphier-ld11-clock";

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+98 −13
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */

/memreserve/ 0x80000000 0x00080000;



/ {

	compatible = "socionext,uniphier-ld20";
@@ -79,35 +79,120 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a72", "arm,armv8";

			reg = <0 0x000>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			clocks = <&sys_clk 32>;

			enable-method = "psci";

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a72", "arm,armv8";

			reg = <0 0x001>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			clocks = <&sys_clk 32>;

			enable-method = "psci";

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu2: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			clocks = <&sys_clk 33>;

			enable-method = "psci";

			operating-points-v2 = <&cluster1_opp>;

		};



		cpu3: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0 0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x80000000>;

			clocks = <&sys_clk 33>;

			enable-method = "psci";

			operating-points-v2 = <&cluster1_opp>;

		};

	};



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@250000000 {

			opp-hz = /bits/ 64 <250000000>;

			clock-latency-ns = <300>;

		};

		opp@275000000 {

			opp-hz = /bits/ 64 <275000000>;

			clock-latency-ns = <300>;

		};

		opp@500000000 {

			opp-hz = /bits/ 64 <500000000>;

			clock-latency-ns = <300>;

		};

		opp@550000000 {

			opp-hz = /bits/ 64 <550000000>;

			clock-latency-ns = <300>;

		};

		opp@666667000 {

			opp-hz = /bits/ 64 <666667000>;

			clock-latency-ns = <300>;

		};

		opp@733334000 {

			opp-hz = /bits/ 64 <733334000>;

			clock-latency-ns = <300>;

		};

		opp@1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			clock-latency-ns = <300>;

		};

		opp@1100000000 {

			opp-hz = /bits/ 64 <1100000000>;

			clock-latency-ns = <300>;

		};

	};



	cluster1_opp: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp@250000000 {

			opp-hz = /bits/ 64 <250000000>;

			clock-latency-ns = <300>;

		};

		opp@275000000 {

			opp-hz = /bits/ 64 <275000000>;

			clock-latency-ns = <300>;

		};

		opp@500000000 {

			opp-hz = /bits/ 64 <500000000>;

			clock-latency-ns = <300>;

		};

		opp@550000000 {

			opp-hz = /bits/ 64 <550000000>;

			clock-latency-ns = <300>;

		};

		opp@666667000 {

			opp-hz = /bits/ 64 <666667000>;

			clock-latency-ns = <300>;

		};

		opp@733334000 {

			opp-hz = /bits/ 64 <733334000>;

			clock-latency-ns = <300>;

		};

		opp@1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			clock-latency-ns = <300>;

		};

		opp@1100000000 {

			opp-hz = /bits/ 64 <1100000000>;

			clock-latency-ns = <300>;

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	clocks {

		refclk: ref {

			compatible = "fixed-clock";
@@ -274,7 +359,7 @@ 
		};



		perictrl@59820000 {

			compatible = "socionext,uniphier-perictrl",

			compatible = "socionext,uniphier-ld20-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;
@@ -290,7 +375,7 @@ 
		};



		soc-glue@5f800000 {

			compatible = "socionext,uniphier-soc-glue",

			compatible = "socionext,uniphier-ld20-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;
@@ -309,9 +394,9 @@ 
		};



		sysctrl@61840000 {

			compatible = "socionext,uniphier-sysctrl",

			compatible = "socionext,uniphier-ld20-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x4000>;

			reg = <0x61840000 0x10000>;



			sys_clk: clock {

				compatible = "socionext,uniphier-ld20-clock";

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