MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs (6241bf6a) · Commits · 戴 / test

AR913x, AR724x and AR933x are the only SoCs where the ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c Invert the logic to make the code compatible with AR95xx Signed-off-by:

Felix Fietkau <nbd@nbd.name> Cc: albeu@free.fr Cc: sergei.shtylyov@cogentembedded.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13257/ Signed-off-by:

Ralf Baechle <ralf@linux-mips.org>

arch/mips/ath79/common.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void)
		{
		ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
		AR71XX_DDR_CTRL_SIZE);
		if (soc_is_ar71xx() \|\| soc_is_ar934x()) {
		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
		ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
		} else {
		if (soc_is_ar913x() \|\| soc_is_ar724x() \|\| soc_is_ar933x()) {
		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
		ath79_ddr_pci_win_base = 0;
		} else {
		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
		ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
		}
		}
		EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);

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